{"title":"高压dmosfet高频电池设计之比较","authors":"N. Thapar, B. J. Baliga","doi":"10.1109/ISPSD.1994.583674","DOIUrl":null,"url":null,"abstract":"To reduce the conduction and switching losses in a MOSFET, it is desirable to reduce its specific on-resistance (R/sub on,sp/) and the specific input capacitance (C/sub in,sp/). In this paper, the Atomic Lattice Layout (ALL) and the Circular Layout (CL) are compared for a high frequency 400 V n-channel MOSFET with the goal of obtaining the lowest R/sub on/C/sub in/ product. The terrace gate design on ALL, with 6000 /spl Aring/ field oxide under the terrace gate region resulted in a R/sub on/C/sub in/ product of 603 /spl Omega/-pf which is nearly 4 times lower than the conventional DMOS design. It was also found to be superior to the same gate design on a CL. In the cell structure with a floating P/sup +/ diffusion, the gate-drain component (C/sub gd/) of the input capacitance (C/sub in/) was reduced by moving the floating P/sup +/ diffusion edge closer to the P-base edge at the expense of increasing the on-resistance. By studying the variation of the R/sub on/C/sub in/ product as a function of the position of the floating P/sup +/ edge, lowest R/sub on/C/sub in/ products of 452 /spl Omega/-pf and 360 /spl Omega/-pf were obtained for the ALL and CL, respectively. Although the R/sub on/C/sub in/ product of this structure is smaller than the terraced gate structures, the specific on-resistance is larger (98 m/spl Omega/-cm/sup 2/ vs 68 m/spl Omega/-cm/sup 2/ for the ALL and 137 m/spl Omega/-cm/sup 2/ vs 86 m/spl Omega/-cm/sup 2/ for the CL), which implies an increase in the die area. It was shown through simulations that the specific on-resistance did not increase appreciably with a reduction in the gate bias from 10 V to 5 V. Hence operation at 5 V gate bias is recommended to reduce the gate switching losses, which increase as the square of the gate drive voltage.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A comparison of high frequency cell designs for high voltage DMOSFETs\",\"authors\":\"N. Thapar, B. J. Baliga\",\"doi\":\"10.1109/ISPSD.1994.583674\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To reduce the conduction and switching losses in a MOSFET, it is desirable to reduce its specific on-resistance (R/sub on,sp/) and the specific input capacitance (C/sub in,sp/). In this paper, the Atomic Lattice Layout (ALL) and the Circular Layout (CL) are compared for a high frequency 400 V n-channel MOSFET with the goal of obtaining the lowest R/sub on/C/sub in/ product. The terrace gate design on ALL, with 6000 /spl Aring/ field oxide under the terrace gate region resulted in a R/sub on/C/sub in/ product of 603 /spl Omega/-pf which is nearly 4 times lower than the conventional DMOS design. It was also found to be superior to the same gate design on a CL. In the cell structure with a floating P/sup +/ diffusion, the gate-drain component (C/sub gd/) of the input capacitance (C/sub in/) was reduced by moving the floating P/sup +/ diffusion edge closer to the P-base edge at the expense of increasing the on-resistance. By studying the variation of the R/sub on/C/sub in/ product as a function of the position of the floating P/sup +/ edge, lowest R/sub on/C/sub in/ products of 452 /spl Omega/-pf and 360 /spl Omega/-pf were obtained for the ALL and CL, respectively. Although the R/sub on/C/sub in/ product of this structure is smaller than the terraced gate structures, the specific on-resistance is larger (98 m/spl Omega/-cm/sup 2/ vs 68 m/spl Omega/-cm/sup 2/ for the ALL and 137 m/spl Omega/-cm/sup 2/ vs 86 m/spl Omega/-cm/sup 2/ for the CL), which implies an increase in the die area. It was shown through simulations that the specific on-resistance did not increase appreciably with a reduction in the gate bias from 10 V to 5 V. Hence operation at 5 V gate bias is recommended to reduce the gate switching losses, which increase as the square of the gate drive voltage.\",\"PeriodicalId\":405897,\"journal\":{\"name\":\"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-05-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.1994.583674\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1994.583674","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
摘要
为了降低MOSFET的传导和开关损耗,需要降低其比导通电阻(R/sub on,sp/)和比输入电容(C/sub in,sp/)。本文对高频400 V n沟道MOSFET的原子点阵布局(ALL)和圆形布局(CL)进行了比较,目的是获得最低的R/sub on/C/sub In /积。阶地栅极在ALL上设计,阶地栅极区域下有6000 /spl Aring/ field oxide, R/sub on/C/sub in/ product为603 /spl Omega/-pf,比传统DMOS设计低近4倍。它也被发现优于相同的闸门设计在一个CL。在具有浮动P/sup +/扩散的电池结构中,通过将浮动P/sup +/扩散边缘移近P基边缘,以增加导通电阻为代价,减小了输入电容(C/sub In /)的栅极漏极分量(C/sub gd/)。通过研究R/sub on/C/sub in/ product随浮P/sup +/边缘位置的变化规律,得到ALL和CL的R/sub on/C/sub in/ product的最低值分别为452 /spl Omega/-pf和360 /spl Omega/-pf。虽然这种结构的R/sub - on/C/sub - in/乘积小于梯级栅极结构,但比导通电阻更大(ALL为98 m/spl Omega/-cm/sup 2/ vs 68 m/spl Omega/-cm/sup 2/, CL为137 m/spl Omega/-cm/sup 2/ vs 86 m/spl Omega/-cm/sup 2/),这意味着模具面积增加。模拟结果表明,栅极偏置从10 V减小到5 V时,导通电阻没有明显增加。因此,建议在5 V栅极偏置下工作,以减少栅极开关损耗,栅极开关损耗随栅极驱动电压的平方而增加。
A comparison of high frequency cell designs for high voltage DMOSFETs
To reduce the conduction and switching losses in a MOSFET, it is desirable to reduce its specific on-resistance (R/sub on,sp/) and the specific input capacitance (C/sub in,sp/). In this paper, the Atomic Lattice Layout (ALL) and the Circular Layout (CL) are compared for a high frequency 400 V n-channel MOSFET with the goal of obtaining the lowest R/sub on/C/sub in/ product. The terrace gate design on ALL, with 6000 /spl Aring/ field oxide under the terrace gate region resulted in a R/sub on/C/sub in/ product of 603 /spl Omega/-pf which is nearly 4 times lower than the conventional DMOS design. It was also found to be superior to the same gate design on a CL. In the cell structure with a floating P/sup +/ diffusion, the gate-drain component (C/sub gd/) of the input capacitance (C/sub in/) was reduced by moving the floating P/sup +/ diffusion edge closer to the P-base edge at the expense of increasing the on-resistance. By studying the variation of the R/sub on/C/sub in/ product as a function of the position of the floating P/sup +/ edge, lowest R/sub on/C/sub in/ products of 452 /spl Omega/-pf and 360 /spl Omega/-pf were obtained for the ALL and CL, respectively. Although the R/sub on/C/sub in/ product of this structure is smaller than the terraced gate structures, the specific on-resistance is larger (98 m/spl Omega/-cm/sup 2/ vs 68 m/spl Omega/-cm/sup 2/ for the ALL and 137 m/spl Omega/-cm/sup 2/ vs 86 m/spl Omega/-cm/sup 2/ for the CL), which implies an increase in the die area. It was shown through simulations that the specific on-resistance did not increase appreciably with a reduction in the gate bias from 10 V to 5 V. Hence operation at 5 V gate bias is recommended to reduce the gate switching losses, which increase as the square of the gate drive voltage.