{"title":"紧凑的非常高电压CMOS兼容双极绝缘体上硅晶体管","authors":"A. Litwin, T. Arnborg","doi":"10.1109/ISPSD.1994.583667","DOIUrl":null,"url":null,"abstract":"A new type of bipolar transistor on SOI material (Silicon-On-Insulator) without buried layer has been fabricated in a standard 1.3 /spl mu/m CMOS process with only few additional mask steps. It is shown by measurements that the I-V characteristics of both pnp and npn transistors are comparable to conventional vertical transistors with buried layer. The voltage capability of devices made in thin silicon layers is substantially high and strongly affected by substrate bias effects. The transistors designed in a few micrometer thick silicon layer have a breakdown voltage BVceo of about 200 volts and also a remarkably high Early voltage, with highest measured value of 4000 V. The transistor will have a strong impact on the feasibility to realise mixed analogue and digital signal circuits with high and low voltage functions on the same chip.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Compact very high voltage CMOS compatible bipolar silicon-on-insulator transistor\",\"authors\":\"A. Litwin, T. Arnborg\",\"doi\":\"10.1109/ISPSD.1994.583667\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new type of bipolar transistor on SOI material (Silicon-On-Insulator) without buried layer has been fabricated in a standard 1.3 /spl mu/m CMOS process with only few additional mask steps. It is shown by measurements that the I-V characteristics of both pnp and npn transistors are comparable to conventional vertical transistors with buried layer. The voltage capability of devices made in thin silicon layers is substantially high and strongly affected by substrate bias effects. The transistors designed in a few micrometer thick silicon layer have a breakdown voltage BVceo of about 200 volts and also a remarkably high Early voltage, with highest measured value of 4000 V. The transistor will have a strong impact on the feasibility to realise mixed analogue and digital signal circuits with high and low voltage functions on the same chip.\",\"PeriodicalId\":405897,\"journal\":{\"name\":\"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-05-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.1994.583667\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1994.583667","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
采用标准的1.3 /spl μ m CMOS工艺制备了一种新型无埋层SOI材料(绝缘体上硅)双极晶体管,仅需少量附加掩膜步骤。测量结果表明,pnp和npn晶体管的I-V特性与传统的埋层垂直晶体管相当。在薄硅层中制造的器件的电压能力基本上很高,并且受到衬底偏置效应的强烈影响。在几微米厚的硅层上设计的晶体管击穿电压BVceo约为200伏,早期电压非常高,最高测量值为4000 V。晶体管将对在同一芯片上实现具有高低电压功能的混合模拟和数字信号电路的可行性产生重大影响。
Compact very high voltage CMOS compatible bipolar silicon-on-insulator transistor
A new type of bipolar transistor on SOI material (Silicon-On-Insulator) without buried layer has been fabricated in a standard 1.3 /spl mu/m CMOS process with only few additional mask steps. It is shown by measurements that the I-V characteristics of both pnp and npn transistors are comparable to conventional vertical transistors with buried layer. The voltage capability of devices made in thin silicon layers is substantially high and strongly affected by substrate bias effects. The transistors designed in a few micrometer thick silicon layer have a breakdown voltage BVceo of about 200 volts and also a remarkably high Early voltage, with highest measured value of 4000 V. The transistor will have a strong impact on the feasibility to realise mixed analogue and digital signal circuits with high and low voltage functions on the same chip.