SOI基板上横向功率器件的热性能

Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI:10.1109/ISPSD.1994.583671

H. Neubrand, R. Constapel, R. Boot, M. Fullmann, A. Boose

{"title":"SOI基板上横向功率器件的热性能","authors":"H. Neubrand, R. Constapel, R. Boot, M. Fullmann, A. Boose","doi":"10.1109/ISPSD.1994.583671","DOIUrl":null,"url":null,"abstract":"Simulated temperature distributions for SOI-structures with various film thicknesses for different operating conditions (on state, turn-off and pulse overload) and different SOI sheet thicknesses (20 /spl mu/m, 5 /spl mu/m) are presented and discussed. The temperature increase was in the range between 5 K and 400 K. The calculated results have been verified experimentally for a fabricated device. An important result is the reduced pulse overload capacity of thin SOI-devices in the 10 /spl mu/s to 100 /spl mu/s range. Consequences for application of SOI-devices are discussed.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"Thermal behaviour of lateral power devices on SOI substrates\",\"authors\":\"H. Neubrand, R. Constapel, R. Boot, M. Fullmann, A. Boose\",\"doi\":\"10.1109/ISPSD.1994.583671\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Simulated temperature distributions for SOI-structures with various film thicknesses for different operating conditions (on state, turn-off and pulse overload) and different SOI sheet thicknesses (20 /spl mu/m, 5 /spl mu/m) are presented and discussed. The temperature increase was in the range between 5 K and 400 K. The calculated results have been verified experimentally for a fabricated device. An important result is the reduced pulse overload capacity of thin SOI-devices in the 10 /spl mu/s to 100 /spl mu/s range. Consequences for application of SOI-devices are discussed.\",\"PeriodicalId\":405897,\"journal\":{\"name\":\"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-05-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.1994.583671\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1994.583671","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 17

摘要

给出并讨论了不同SOI薄膜厚度(20 /spl mu/m、5 /spl mu/m)下不同工作条件(导通、关断和脉冲过载)下不同薄膜厚度SOI结构的模拟温度分布。升温幅度在5k ~ 400k之间。计算结果已在实验中得到验证。一个重要的结果是，在10 /spl mu/s到100 /spl mu/s范围内，薄soi器件的脉冲过载能力降低。讨论了soi器件应用的后果。

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Thermal behaviour of lateral power devices on SOI substrates

Simulated temperature distributions for SOI-structures with various film thicknesses for different operating conditions (on state, turn-off and pulse overload) and different SOI sheet thicknesses (20 /spl mu/m, 5 /spl mu/m) are presented and discussed. The temperature increase was in the range between 5 K and 400 K. The calculated results have been verified experimentally for a fabricated device. An important result is the reduced pulse overload capacity of thin SOI-devices in the 10 /spl mu/s to 100 /spl mu/s range. Consequences for application of SOI-devices are discussed.

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Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics

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