Compact very high voltage CMOS compatible bipolar silicon-on-insulator transistor

Abstract

A new type of bipolar transistor on SOI material (Silicon-On-Insulator) without buried layer has been fabricated in a standard 1.3 /spl mu/m CMOS process with only few additional mask steps. It is shown by measurements that the I-V characteristics of both pnp and npn transistors are comparable to conventional vertical transistors with buried layer. The voltage capability of devices made in thin silicon layers is substantially high and strongly affected by substrate bias effects. The transistors designed in a few micrometer thick silicon layer have a breakdown voltage BVceo of about 200 volts and also a remarkably high Early voltage, with highest measured value of 4000 V. The transistor will have a strong impact on the feasibility to realise mixed analogue and digital signal circuits with high and low voltage functions on the same chip.