H. Neubrand, R. Constapel, R. Boot, M. Fullmann, A. Boose
{"title":"Thermal behaviour of lateral power devices on SOI substrates","authors":"H. Neubrand, R. Constapel, R. Boot, M. Fullmann, A. Boose","doi":"10.1109/ISPSD.1994.583671","DOIUrl":null,"url":null,"abstract":"Simulated temperature distributions for SOI-structures with various film thicknesses for different operating conditions (on state, turn-off and pulse overload) and different SOI sheet thicknesses (20 /spl mu/m, 5 /spl mu/m) are presented and discussed. The temperature increase was in the range between 5 K and 400 K. The calculated results have been verified experimentally for a fabricated device. An important result is the reduced pulse overload capacity of thin SOI-devices in the 10 /spl mu/s to 100 /spl mu/s range. Consequences for application of SOI-devices are discussed.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1994.583671","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17
Abstract
Simulated temperature distributions for SOI-structures with various film thicknesses for different operating conditions (on state, turn-off and pulse overload) and different SOI sheet thicknesses (20 /spl mu/m, 5 /spl mu/m) are presented and discussed. The temperature increase was in the range between 5 K and 400 K. The calculated results have been verified experimentally for a fabricated device. An important result is the reduced pulse overload capacity of thin SOI-devices in the 10 /spl mu/s to 100 /spl mu/s range. Consequences for application of SOI-devices are discussed.