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2008 International SoC Design Conference最新文献

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A tessellator based on a vertex shader for bandwidth-efficient mobile 3D graphics 一个基于顶点着色器的tessellator，用于带宽高效的移动3D图形
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815753
Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, L. Kim
{"title":"A tessellator based on a vertex shader for bandwidth-efficient mobile 3D graphics","authors":"Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, L. Kim","doi":"10.1109/SOCDC.2008.4815753","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815753","url":null,"abstract":"A tessellation-enabled shader (TES), 1/250 memory bandwidth saving geometry processor, is proposed for a mobile 3D graphics engine. On-chip vertex generation of tessellation is implemented with 6.2% additional logic gate to a conventional vertex shader. An optimized vector dot product unit, a slim special function unit, and a unified data fetch unit reduce 25.6% of area. Dual-core of TES is fabricated using 0.18 um CMOS technology and processes 120 Mvertices/s at 100 MHz while consuming 272 mW of power.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123934887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design trend of energy-efficient CAMs 节能凸轮的设计趋势
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815565
Jinn-Shyan Wang, Chao-Ching Wang, Tai-An Chen
{"title":"Design trend of energy-efficient CAMs","authors":"Jinn-Shyan Wang, Chao-Ching Wang, Tai-An Chen","doi":"10.1109/SOCDC.2008.4815565","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815565","url":null,"abstract":"Several state-of-the-art CAM designs are reviewed and studied in this work. Reviews are given in three aspects, including the match-line design, the search-line design, and application-specific designs. Parts of these CAMs are redesigned based on a 90 nm CMOS technology, and evaluation results when they are operated from a subthreshold VDD to a normal high VDD are reported. These results indicate that a new sub-threshold CAM design is needed in the future if a more energy-efficient CAM is pursued.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"01 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129403298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new scheduling technique based on Dynamic Voltage Scaling for MPSoC 一种基于动态电压缩放的MPSoC调度新技术
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815687
Chang-Woo Park, Kyung-Woo Noh, Seok-Yoon Kim
{"title":"A new scheduling technique based on Dynamic Voltage Scaling for MPSoC","authors":"Chang-Woo Park, Kyung-Woo Noh, Seok-Yoon Kim","doi":"10.1109/SOCDC.2008.4815687","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815687","url":null,"abstract":"The DVS(Dynamic Voltage Scaling) technique is the method to reduce the dynamic energy consumption. Using slack times, it extends the execution time of big load operations by changing frequency and voltage of variable voltage processors. Many researches have been going on to control the energy consumption of the processors and the data transmission among processors by controlling the bandwidth to reduce the energy consumption of the entire system. Since operations in multiprocessor systems have the data dependency between processors, however, the DVS techniques devised for single processors are not suitable to improve the energy efficiency of multiprocessor systems. We propose a new scheduling algorithm based on DVS for increasing energy efficiency of multiprocessor systems. The proposed DVS-based scheduling algorithm can improve the energy efficiency of entire systems because it controls frequency and voltages while considering the data dependency among processors.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129439215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analysis on light attenuation through multi-metal-layers for CMOS image sensors on system LSIs 系统lsi上CMOS图像传感器多金属层光衰减分析
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815581
Yun-Kyung Kim, M. Ikeda, K. Asada
{"title":"Analysis on light attenuation through multi-metal-layers for CMOS image sensors on system LSIs","authors":"Yun-Kyung Kim, M. Ikeda, K. Asada","doi":"10.1109/SOCDC.2008.4815581","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815581","url":null,"abstract":"This paper proposes a method for analysis of spectral characteristics on multilayer interconnection. With CMOS technology's downscaling, interconnect layers are multi-stratified since the number of metal levels has increased. However, this multilayer interconnection affects sensitivity of CMOS image sensors. To evaluate the effect on the multilayer interconnect of standard CMOS process technologies, we have developed a method for calculating transferred light intensity through the multilayer interconnect. We show the calculation results in case of standard CMOS 65 nm, 90 nm, 0.18 mum, 0.35 mum, 0.6 mum, and 1.2 mum process technologies.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"01 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129048878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort 2.7Gbps和1.62Gbps双模时钟和数据恢复DisplayPort
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815672
Seungwon Lee, Jae-Wook Yoo, Jin-Ku Kang
{"title":"A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort","authors":"Seungwon Lee, Jae-Wook Yoo, Jin-Ku Kang","doi":"10.1109/SOCDC.2008.4815672","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815672","url":null,"abstract":"This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7 Gbps and 1.62 Gbps for DisplayPort sink device. This CDR uses the half-rate linear phase detector (PD). A voltage-controlled oscillator (VCO) is proposed to change the operating frequency of half-rate clock with a ldquoModerdquo switch control. This work is implemented 0.18 mum CMOS process. The device exhibits peak-to-peak jitters of 12 ps and 14 ps in the recovered clock with random data inputs. The power dissipation is 81 mW from a 1.8 V supply.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132408697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PDSDL: A dynamic System Description Language PDSDL:动态系统描述语言
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815608
Mi Zhang, Shi-liang Tu, Zhilei Chai
{"title":"PDSDL: A dynamic System Description Language","authors":"Mi Zhang, Shi-liang Tu, Zhilei Chai","doi":"10.1109/SOCDC.2008.4815608","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815608","url":null,"abstract":"In this paper, we present a new System Description Language (SDL): PDSDL (Python based dynamic system description language). It is used in system modeling and verification, even it can be synthesized to a hardware description language (e.g. Verilog) for implementation on FPGA or ASIC. PDSDL promises to be more flexible and productive than prevalent SystemC. (1) Different from SystemC, it uses Python language other than C/C++ to enjoy the massive merits. (2)Though they both add necessary system related properties to a general-purpose language to achieve their goals, they differ greatly in essence. PDSDL innovatively proposes the dynamic system concept. The modeling, verification and synthesis all rely on the properties of the dynamic changeable system, not the static description in related storage. In addition, Dynamic system enables more efficient design-space exploration by using artificial intelligent method. As a use case, we apply PDSDL to our real-time embedded Java processor design. From our experience, it can speed up productivity at least 5. In addition, the difficulty to develop further tool chain is reduced.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"106 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130434395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Automatic generation of diagrams for system-on-chip architectures 为片上系统架构自动生成图表
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815637
Younbo Oh, Kyosun Kim, Eunchoul Lee, Myung-Gun Kim
{"title":"Automatic generation of diagrams for system-on-chip architectures","authors":"Younbo Oh, Kyosun Kim, Eunchoul Lee, Myung-Gun Kim","doi":"10.1109/SOCDC.2008.4815637","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815637","url":null,"abstract":"The automatic generation of diagrams for gate networks has been practically used in the HDL based design for decades. Unfortunately, these diagrams are losing their popularity since they have failed to satisfy the requirements that have been newly brought up in the system level. The related issues include (i) the irregularity of blocks, (ii) the large number of block pins, and (iii) the complicated interconnection which is domineered by the bus architectures. These buses are globally distributed and shared by most blocks. The conventional topological ordering which assumes the left-to-right signal flows is simply not working, any more. We propose a fish-bone style topological construct which is popular to hand-drawn diagrams, but imposes a new combinatorial problem on the CAD research and development. A heuristic algorithm has been developed and implemented to solve this problem and validated on industrial- strength system-level designs.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121612549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Leveraging CMOS design tools for QCA designs 利用CMOS设计工具进行QCA设计
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815714
Kyosun Kim, Younbo Oh, R. Karri, A. Orailoglu
{"title":"Leveraging CMOS design tools for QCA designs","authors":"Kyosun Kim, Younbo Oh, R. Karri, A. Orailoglu","doi":"10.1109/SOCDC.2008.4815714","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815714","url":null,"abstract":"This paper proposes a radical approach to designing nanoscale quantum dot cellular automata (QCA) designs by leveraging CMOS design tools such as those used for logic validation. Based on design rules that guarantee deterministic digital behavior of QCA designs, we identified a finite set of legal arrangements for QCA cells. These cell arrangements can be composed to yield robust QCA building block gates (majority gate and inverters) and interconnect structures. On one hand, such a hierarchical building blocks approach can be used to synthesize large scale, robust QCA designs. On the other hand, as shown in this paper, such a hierarchical building blocks approach can be used to check if QCA designs follow the robust design rules. If so, the implemented digital logic function can be extracted, translated into an equivalent Verilog or VHDL netlist, and validated using commercial CMOS design validation tools. Towards demonstrating the proposed approach, we designed a 2-bit QCA adder, extracted the digital logic, stored it in a common engineering database (OpenAccess) and validated the functionality using ModelSim CMOS simulator.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121045484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A study of detection algorithm for DAA regulation of Korea using MB-OFDM UWB receiver 基于MB-OFDM UWB接收机的韩国DAA调节检测算法研究
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815674
Cheol-Ho Shin, Byounghak Kim, Sangsung Choi
{"title":"A study of detection algorithm for DAA regulation of Korea using MB-OFDM UWB receiver","authors":"Cheol-Ho Shin, Byounghak Kim, Sangsung Choi","doi":"10.1109/SOCDC.2008.4815674","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815674","url":null,"abstract":"This paper analyzed the performance of a detection algorithm using MB-OFDM UWB receiver based on silent time when the victim signal is received by detection limit of -80 dBm/MHz proposed in Korea for DAA. Simulation results show that the performance of the proposed detection algorithm is enough to detect the victim signal with 95% detection probability within the +/-0.5 dB error range if repeat Number over 4 is used.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122502119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of high-performance unified motion estimation IP for H.264/MPEG-4 video CODEC 面向H.264/MPEG-4视频编解码器的高性能统一运动估计IP设计
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815596
Dong-yeob Chun, Joonho Kim, Seonyoung Lee, Kyeongsoon Cho
{"title":"Design of high-performance unified motion estimation IP for H.264/MPEG-4 video CODEC","authors":"Dong-yeob Chun, Joonho Kim, Seonyoung Lee, Kyeongsoon Cho","doi":"10.1109/SOCDC.2008.4815596","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815596","url":null,"abstract":"Motion estimation for H.264/MPEG-4 video CODEC is very complex and requires a huge amount of computational effors because it uses multiple reference frames and variable block sizes. This paper describes the architecture and design of high-performance unified motion estimation IP based on fast algorithms for multiple reference frame selection, block matching with variable search window, block mode decision, and motion vector estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The resultant circuit consists of 77,600 logic gates and 4 32times8times32-bit dual-port SRAM's. It has the maximum operating frequency of 161MHz and can process up to 51 D1 (720times480) color image frames per second.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122591808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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