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Selective multiplexer-removal algorithm for lowering power consumption of circuits 降低电路功耗的选择性多路器去除算法
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815690
Chi-Hoon Shin, Myeonghoon Oh, Young-Woo Kim, Sungnam Kim, Seongwoon Kim
{"title":"Selective multiplexer-removal algorithm for lowering power consumption of circuits","authors":"Chi-Hoon Shin, Myeonghoon Oh, Young-Woo Kim, Sungnam Kim, Seongwoon Kim","doi":"10.1109/SOCDC.2008.4815690","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815690","url":null,"abstract":"In this paper we propose an algorithm about aggressive, but partial removal of multiplexers used for sharing functional units (FUs). By eliminating some multiplexers and duplicating the FU related, the proposed algorithm could be more advantageous for low power circuits than just keeping the multiplexers. To determine whether a removal of a group of multiplexers is beneficial or not, we compared a FU with multiplexers to multiple replications of the FU without any multiplexer under various conditions. Through the experiments, we aggregated information to be used for finding appropriate multiplexers to be extricated from circuit netlist; using the information, we built an automated algorithm to remove particular multiplexers; we applied it to a netlist of 16 bit processor. The processor that is newly generated by the algorithm consumed average about 12% less power than the initial processor.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124482000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Crosstalk avoidance method considering multi-aggressors 考虑多干扰源的串扰避免方法
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815708
Sibaek Jung, Naeun Zang, Eunsuk Park, Juho Kim
{"title":"Crosstalk avoidance method considering multi-aggressors","authors":"Sibaek Jung, Naeun Zang, Eunsuk Park, Juho Kim","doi":"10.1109/SOCDC.2008.4815708","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815708","url":null,"abstract":"This As manufacturing technology scales to smaller dimensions, wire size is increasing and spacing between wires is decreasing, the influence of interconnect becomes dominant factor. Coupling capacitance between wires induces crosstalk. Crosstalk causes functional and temporal problem. In this paper, we propose timing window shift method considering multi-aggressors to reduce delay degradation. We assume that crosstalk induced delay degradation is proportional to coupling capacitance and timing window overlap. In this assumption, we model Aggressive Factor which represents the amount of crosstalk induced delay degradation. Proposed method is experimented with ISCAS85 benchmark circuit. We have a result that average of 4.85% crosstalk induced delay degradation minimization.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128142434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
System anlaysis of power-aware H.264/AVC encoder based on fast inter prediction 基于快速互预测的功率感知H.264/AVC编码器系统分析
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815616
Yeong-Kang Lai, Lien-Fei Chen, Shin-Ping Yang
{"title":"System anlaysis of power-aware H.264/AVC encoder based on fast inter prediction","authors":"Yeong-Kang Lai, Lien-Fei Chen, Shin-Ping Yang","doi":"10.1109/SOCDC.2008.4815616","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815616","url":null,"abstract":"In H.264 encoder system, the power dissipation of inter prediction occupies a quite large part. For low-power and power-aware system design, efficient fast inter prediction algorithms are the significant techniques to reduce the power consumption. In this paper, a system-level power-aware algorithm based on the early termination scheme of H.264 inter prediction is proposed for the power-aware H.264 encoder. The proposed early termination scheme for H.264 motion estimation is based on the statistical analysis of the transform coefficients. Due to the theoretical model, we develop a power-aware adaptive scheme with multiple thresholds derived from the statistical model to early terminate the motion estimation (ME) operations. Moreover, the proposed inter mode pre-decision is also utilized to early determine the best inter mode at integer motion estimation (IME) stage to substantially decrease the computational cycle counts of the fractional motion estimator (FME) and carry off the motion vector predictor (MVP). According to the experimental results, our system level fast inter prediction design methodology not only preserves fine RD performance but also eliminates the unnecessary operations in both IME stage and FME stage to realize the power-aware H.264 encoder system.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132787548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An all-digital phase-locked loop with fast acquisition and low jitter 全数字锁相环，具有快速采集和低抖动
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815626
Jun Zhao, Yong-Bin Kim
{"title":"An all-digital phase-locked loop with fast acquisition and low jitter","authors":"Jun Zhao, Yong-Bin Kim","doi":"10.1109/SOCDC.2008.4815626","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815626","url":null,"abstract":"An all-digital phase-locked loop that achieves fast acquisition and low jitter was developed for high-speed clock generation. By employing a time-to-digital converter (TDC), the frequency difference is precisely measured and converted to the control word of the digital oscillator. Using this feature, the ADPLL has a faster lock-in time than previous digital phaselocked loops. The ADPLL was implemented using a 0.9 V 32 nm practical transistor model (PTM). The simulation results show that the proposed ADPLL achieves 5 and 10 reference cycles of frequency and phase acquisitions at 700 MHz with peak to peak jitter < 53 ps.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131054821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low power digital pixel sensor with a dynamically biased ADC 具有动态偏置ADC的低功耗数字像素传感器
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815584
Xiajun Wu, A. Bermak
{"title":"A low power digital pixel sensor with a dynamically biased ADC","authors":"Xiajun Wu, A. Bermak","doi":"10.1109/SOCDC.2008.4815584","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815584","url":null,"abstract":"In this paper, a low power CMOS image sensor using DPS scheme is proposed. A sub-threshold control unit is used in order to enable or disable the pixel level ADC depending on the photodiode sensing voltage, hence enabling to save the static power needed to operate the pixel level ADC. Results show that up to 90% power saving is achieved when compared with the conventional digital pixel sensor. To compensate for the non-linearity of the proposed time-domain ADC a clock modulation compensation scheme is proposed which can be fully implemented in digital. The sensor was implemented in 0.35 mum CMOS process and the sensor operation is successfully tested.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130739273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A unified transform unit for H.264 H.264的统一变换单元
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815701
Sehyun Song, Changwoo Seo, Kichul Kim
{"title":"A unified transform unit for H.264","authors":"Sehyun Song, Changwoo Seo, Kichul Kim","doi":"10.1109/SOCDC.2008.4815701","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815701","url":null,"abstract":"This paper presents a unified transform unit that can efficiently perform forward integer transform, quantization, dequantization, inverse integer transform, and Hadamard transform in H.264/AVC. To reduce hardware cost, the proposed architecture uses shifters, adder/subtractors instead of multipliers for quantization and de-quantization, and reuses 1-D transform unit for all supporting transforms. Hardware utilization is maximized to achieve required performance with low cost. It takes about 250 cycles to perform forward integer transform, quantization, de-quantization, and inverse integer transform for a macroblock, and additional 35 cycles for forward and inverse Hadamard transforms. The architecture can process about 6,000 frames of QCIF at 150 MHz. The unified transform unit can be widely used in mobile devices.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131002702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Varactor tunned high-Q aictive inductor with broadband tuning range 宽调谐范围的变容调谐高q有源电感
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815740
Kyungjun Song, Y. Jeong, Heungjae Choi
{"title":"Varactor tunned high-Q aictive inductor with broadband tuning range","authors":"Kyungjun Song, Y. Jeong, Heungjae Choi","doi":"10.1109/SOCDC.2008.4815740","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815740","url":null,"abstract":"This paper presents a novel high-Q inductor using conventional grounded active inductor and feedback parallel resonance circuit. The proposed high-Q inductor using tunable LC resonance circuit (HITR) consists of the conventional active grounded inductor and feedback parallel resonance circuit which is composed of low-Q spiral inductor and MOS varactor. The novelty of the proposed structure is based on the increase of Q-factor by feeding parallel resonance circuit into gyrator structure. The high-Q inductor is fabricated by 0.18 mum Hynix CMOS technology. The fabricated inductor shows inductance of above 45 nH and Q-factor of over 640 around 5.4 GHz.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133188796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Linear wideband CMOS LNA for 3–5 GHZ UWB systems 一种用于3 - 5ghz超宽带系统的线性宽带CMOS LNA
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815706
A. Mirvakili, M. Yavari
{"title":"A Linear wideband CMOS LNA for 3–5 GHZ UWB systems","authors":"A. Mirvakili, M. Yavari","doi":"10.1109/SOCDC.2008.4815706","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815706","url":null,"abstract":"A linear wideband low noise amplifier (LNA) that utilizes distortion canceling is proposed in this paper. It improves the linearity and contemporarily minimizes the effect of 2nd-order interaction. The deteriorating effect of the input matching network on the noise figure is also discussed. The proposed LNA designed in a 0.13mum standard RFCMOS technology, targets 3-5 GHZ UWB systems. The 3-dB bandwidth of LNA is 2.88 - 5.1 GHZ. The proposed LNA achieves a power gain of 11dB, better than 10 dB input matching, the minimum noise figure of 1.8 dB, and the input IP3 of +4.4 dBm, while dissipating only 5.2 mW from a single 1.2 V power supply.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115397002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
12-bit 80MSPS double folding/interpolation A/D converter 12位80MSPS双折叠/插值A/D转换器
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815720
Byungill Kim, Daeyun Kim, Jooho Hwang, Junho Moon, Minkyu Song
{"title":"12-bit 80MSPS double folding/interpolation A/D converter","authors":"Byungill Kim, Daeyun Kim, Jooho Hwang, Junho Moon, Minkyu Song","doi":"10.1109/SOCDC.2008.4815720","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815720","url":null,"abstract":"In this paper, a CMOS analog-to-digital converter (ADC) with a 12-bit 80 MSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a folding ADC with a double folding and interpolating structure. An even folding circuit technique for the high resolution and high speed ADC are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18 um 1-poly 6-metal CMOS technology. The active area is 1.6 mm2 and 195 mw at 1.8 V power supply. The DNL and INL are within plusmn4/plusmn4LSB, respectively. The measured result of SNDR is 46 dB, when Fin=1MHz at Fs=80 MHz.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124501088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
SoC platform design with multi-channel bus architecture 多通道总线架构的SoC平台设计
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815743
Younjin Jung, Ok Kim, Byoungyup Lee, Hongkyun Jung, K. Ryoo
{"title":"SoC platform design with multi-channel bus architecture","authors":"Younjin Jung, Ok Kim, Byoungyup Lee, Hongkyun Jung, K. Ryoo","doi":"10.1109/SOCDC.2008.4815743","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815743","url":null,"abstract":"We have designed an SoC platform with a multi-channel bus architecture which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of OpenRISC 1200 processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DMA, AC97 controller, debug interface and UART. The crossbar on-chip bus supports up to 8 masters and 16 slaves, WISHBONE compatible peripheral IPs and allows more than one master to use the bus because of multiple channels. The proposed platform is implemented on Altera's EP2C70F672 FPGA device. As a result of the test program, the proposed platform has better efficiency by 26.58% than the SoC platform with shared bus on-chip bus.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123622342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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