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2008 International SoC Design Conference最新文献

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Design of application specific processor for H.264 inverse transform and quantization H.264反变换与量化专用处理器的设计
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815683
Jae-Jin Lee, Seongmo Park, N. Eum
{"title":"Design of application specific processor for H.264 inverse transform and quantization","authors":"Jae-Jin Lee, Seongmo Park, N. Eum","doi":"10.1109/SOCDC.2008.4815683","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815683","url":null,"abstract":"This paper proposes a new application specific processor and compiler targeting H.264 inverse transform and inverse quantization. They are based on the 6-stage pipelined dual issue VLIW+SIMD architecture, efficient instructions for inverse transform and inverse quantization, and compiler mapping techniques such as CKF (compiler known function), inline assembly and CGD (code generator description). The proposed architecture whose approximate gate count is about 130 K runs at 100 MHz. Compared to the ARM1020E processor, the proposed architecture and compiler result in about 20~46% improvement in terms of total cycles as well as smaller hardware complexity.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122708637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A synchronous DRAM controller for an H.264/AVC encoder 用于H.264/AVC编码器的同步DRAM控制器
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815697
Gyoung-Hwan Hyun, Yongseok Jin, Jin-Su Jung, Seongyoon Kim, Hyuk-Jae Lee
{"title":"A synchronous DRAM controller for an H.264/AVC encoder","authors":"Gyoung-Hwan Hyun, Yongseok Jin, Jin-Su Jung, Seongyoon Kim, Hyuk-Jae Lee","doi":"10.1109/SOCDC.2008.4815697","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815697","url":null,"abstract":"In order to use a synchronous dynamic RAM (SDRAM) as the off-chip memory of an H.264/AVC encoder, this paper proposes an efficient SDRAM memory controller with an asynchronous bridge. With the proposed architecture, the SDRAM bandwidth is increased by making the operation frequency of an external SDRAM higher than that of the hardware accelerators of an H.264/AVC encoder. Experimental results show that the encoding speed is increased by 30.5% when the SDRAM clock frequency is increased from 100 MHz to 200 MHz while the H.264/AVC hardware accelerators operate at 100 MHz.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114583753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CMOS OTA compensating transconductance linearity with PMOS path CMOS OTA补偿跨导线性与PMOS路径
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815564
Doo-Hwan Kim, Kyoung-Rok Cho
{"title":"CMOS OTA compensating transconductance linearity with PMOS path","authors":"Doo-Hwan Kim, Kyoung-Rok Cho","doi":"10.1109/SOCDC.2008.4815564","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815564","url":null,"abstract":"This paper describes a modified linear operational transconductance amplifier (OTA). We employ the PMOS input stage and PMOS mobility compensation circuit that combines the transistor paths operating at the triode region and subthreshold region that it extends input range to 50% of supply voltage. The circuit enhances linearity of the transconductance (Gm) under the wide input voltage range. The OTA is implemented using a 0.18-mum n-well 1P5M CMOS process under 1.8-V supply. The proposed OTA shows 1% Gm variation and the total harmonic distortion (THD) of below -43-dB under the input range of plusmn0.9-V.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117030157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ODALRISC: A small, low power, and configurable 32-bit RISC processor ODALRISC:一种小型、低功耗、可配置的32位RISC处理器
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815732
Imyong Lee, Dongwook Lee, Kiyoung Choi
{"title":"ODALRISC: A small, low power, and configurable 32-bit RISC processor","authors":"Imyong Lee, Dongwook Lee, Kiyoung Choi","doi":"10.1109/SOCDC.2008.4815732","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815732","url":null,"abstract":"Configurable processor has become popular recently, since it can be easily configured and extended to increase the performance without losing the flexibility of the programmable processor. In the era of MP-SoC, the base versions of configurable processors need to be small and low power consuming because many processors are extended and placed on a single chip and so each processor should be as efficient as possible containing only the functional units and instructions necessary for carrying out the specific task assigned to the processor. In this paper, we present the ODALRISC processor, which is an ultra small and low power consuming configurable 32-bit RISC processor. The base version is synthesized using 0.18 mum technology, taking less than 16 k gates and consuming power less than 0.1 mW/MHz.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117268458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Implementing the component-based software engineering in embedded systems 在嵌入式系统中实现基于组件的软件工程
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815656
Mohammed Abdallah
{"title":"Implementing the component-based software engineering in embedded systems","authors":"Mohammed Abdallah","doi":"10.1109/SOCDC.2008.4815656","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815656","url":null,"abstract":"It is thought that the component-based software engineering can not be used in the embedded systems. This thought is the result of the features of embedded systems. Embedded systems have some unique concerns such as resource constraints, real-time or dependability requirements. These issues make using the component-based software engineering into the embedded systems field more difficult. The aim of this work is to show that it possible to make use of component-based concept in the embedded systems. This paper considers the basic overview of component-based model and general issues about embedded systems. The core issue is providing an example showing that how useful to implement an embedded system using the component-based software engineering.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128590034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A concurrent dual-band CMOS low-noise amplifier for ISM-band application 一种用于ism波段应用的并发双频CMOS低噪声放大器
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815733
Heesauk Jhon, Hakchul Jung, M. Koo, Hyungcheol Shin
{"title":"A concurrent dual-band CMOS low-noise amplifier for ISM-band application","authors":"Heesauk Jhon, Hakchul Jung, M. Koo, Hyungcheol Shin","doi":"10.1109/SOCDC.2008.4815733","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815733","url":null,"abstract":"A dual-band CMOS low-noise amplifier (LNA) for ISM-band application is reported. For low power and dual band operation, the designed LNA adopts a positive-feedback LC-ladder network. Moreover, for cost effective approach, the LNA has been fabricated using a 0.18-mum mixed-signal CMOS process. The implemented LNA shows gain of 8.3 dB and 11.2 dB, and noise figure (NF) of 6.1 dB and 6.6 dB at 19 GHz and 25 GHz, respectively. The proposed LNA exhibits 8.1 mW power consumption from 0.8 V supply and the active chip area including pad is about 720 times 460 mum2.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123892984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
100-Gb/s three-parallel Reed-Solomon based foward error correction architecture for optical communications 基于100 gb /s三并行Reed-Solomon的光通信前向纠错架构
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815623
Hanho Lee, Chang-Seok Choi, Jongyoon Shin, Je-Soo Ko
{"title":"100-Gb/s three-parallel Reed-Solomon based foward error correction architecture for optical communications","authors":"Hanho Lee, Chang-Seok Choi, Jongyoon Shin, Je-Soo Ko","doi":"10.1109/SOCDC.2008.4815623","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815623","url":null,"abstract":"This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-mum CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300 MHz and has a throughput of 115-Gb/s for 0.13-mum CMOS technology.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121257344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Reusable platform design methodology for SoC integration and verification SoC集成与验证的可重用平台设计方法
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815577
Kwang-Hyun Cho, Jaebeom Kim, Euibong Jung, Sik Kim, Zhenmin Li, Young-Rae Cho, Byeong Min, Kyu-Myung Choi
{"title":"Reusable platform design methodology for SoC integration and verification","authors":"Kwang-Hyun Cho, Jaebeom Kim, Euibong Jung, Sik Kim, Zhenmin Li, Young-Rae Cho, Byeong Min, Kyu-Myung Choi","doi":"10.1109/SOCDC.2008.4815577","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815577","url":null,"abstract":"Today system-on-a-chip (SoC) is like a black hole which draws all the important IP/cores in a digital system. Current SoC design methodologies are no longer adequate to meet the challenges of SoC design productivity, design quality and diminishing time-to-market window. This paper describes an innovative SoC platform integration and verification design methodology to enhance design productivity based on IP reuse and IP-XACT standard. Platform integrator including RPTKit (reusable platform toolkit) is developed to improve the efficiency and reliability in platform integration, and platform verifier to improve verification setup time and work efficiency. Several cases of SoC platform designs substantiate the validity and capability of the platform integrator and verifier, which reduced the total SoC integration and verification time by more than 30%.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114331229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Scheduling considering bit level delays 考虑位级延迟的调度
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815639
Jiwoong Kim, Hyunchul Shin
{"title":"Scheduling considering bit level delays","authors":"Jiwoong Kim, Hyunchul Shin","doi":"10.1109/SOCDC.2008.4815639","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815639","url":null,"abstract":"A new scheduling method considering bit level delays for high level synthesis is proposed. Conventional bit level delay computation for high-level synthesis was usually limited for specific resources. However, we have developed an efficient bit level delay computation method which is applicable to various resources, in this research. This method is applied to scheduling. The scheduling algorithm is based on list scheduling and executes chaining considering bit level delays. Furthermore, multicycle chaining can be allowed to improve performance under resource constraints. Experimental results on several well-known DSP examples show that our method improves the performance of the results by 14.7% on the average.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121621950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scan order decision algorithm for improving the reliability of PDP data drivers 提高PDP数据驱动可靠性的扫描顺序决策算法
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815610
Doo Youn Ka, Jae Woon Lee, M. Park, Young Hwan Kim
{"title":"Scan order decision algorithm for improving the reliability of PDP data drivers","authors":"Doo Youn Ka, Jae Woon Lee, M. Park, Young Hwan Kim","doi":"10.1109/SOCDC.2008.4815610","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815610","url":null,"abstract":"This paper proposes a new scan method to protect the data drivers of the plasma display panel from the damage caused by excessive signal switching. The proposed method reduces the signal switching numbers of the data driver by selecting an optimal scan order adaptively for a given input image. The proposed method computes the optimal scan order by mapping the problem onto an traveling salesman problem. In case of pathological benchmark images, the proposed method reduced the switching number by up to 99.8~99.86%, when compared to the existing scan methods.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114697984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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