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A new approach for circuit design optimization using Genetic Algorithm 基于遗传算法的电路设计优化新方法
2008 International SoC Design Conference Pub Date : 2008-12-01 DOI: 10.1109/SOCDC.2008.4815652
Zhiguo Bao, T. Watanabe
{"title":"A new approach for circuit design optimization using Genetic Algorithm","authors":"Zhiguo Bao, T. Watanabe","doi":"10.1109/SOCDC.2008.4815652","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815652","url":null,"abstract":"A circuit designed by human often results in very complex hardware architectures, requiring a large amount of manpower and computational resources. A wider objective is used to find novel solutions to design such complex architectures so that system functionality and performance may not be compromised. Design automation using reconfigurable hardware and evolutionary algorithms (EA), such as genetic algorithm (GA), is one of the methods to tackle this issue. This concept applies the notion of Evolvable Hardware (EHW) to the problem domain such as novel design solutions and circuit optimization. EHW is a new field about the use of EA to synthesize a circuit. EA manipulates a population of individuals where each individual describes how to construct a candidate for a good circuit. Each circuit is assigned a fitness, which indicates how well a candidate satisfies the design specification. EA uses stochastic operators repeatedly to evolve new circuit configurations from existing ones, and a resultant circuit configuration will exhibit a desirable behavior. In this paper, optimum circuit design by using GA with fitness function composed of circuit complexity, power and time delay is proposed, and its effectiveness is shown by simulations.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115799798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations 双电压和功率门控混合设计，降低电压变化时的泄漏功率
2008 International SoC Design Conference Pub Date : 2008-12-01 DOI: 10.1109/SOCDC.2008.4815634
T. Shirai, K. Usami
{"title":"Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations","authors":"T. Shirai, K. Usami","doi":"10.1109/SOCDC.2008.4815634","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815634","url":null,"abstract":"Increase in leakage power and Vth variation is a critical concern in leading-edge CMOS technology. Traditional dual Vth design with the worst corner model becomes difficult to achieve for low leakage because delay variation of high Vth cell is increased significantly by Vth variation. In this paper, we demonstrated that a power gated cell is more tolerant in delay variation than high Vth cell in 45 nm technology. We propose hybrid design technique to use power gated cells in the dual Vth circuit to reduce standby leakage without causing performance degradation. Also, we developed an optimization methodology based on simulated annealing. The proposed technique was applied to ISCAS'85 benchmark circuits. Standby leakage power was reduced by 44% on average over the conventional dual Vth design.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133074085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A single cycle accessible two-level cache architecture for reducing the energy consumption of embedded systems 一种用于降低嵌入式系统能耗的单周期可访问的两级缓存架构
2008 International SoC Design Conference Pub Date : 2008-12-01 DOI: 10.1109/SOCDC.2008.4815604
S. Yamaguchi, T. Ishihara, H. Yasuura
{"title":"A single cycle accessible two-level cache architecture for reducing the energy consumption of embedded systems","authors":"S. Yamaguchi, T. Ishihara, H. Yasuura","doi":"10.1109/SOCDC.2008.4815604","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815604","url":null,"abstract":"Employing a small L0-cache between an MPU core and an L1-cache is one of the most promising approaches for reducing the energy consumption of memory subsystems. Since the L0-cache is small, if there is a hit, the energy consumption will be reduced. On the other hand, if there is a miss, one extra cycle is required to access the L1-cache. This leads to a degradation of the processor performance. For resolving this problem, a single cycle accessible two-level cache (STC) architecture is proposed in this paper. This architecture makes it possible to access to both the L0 and the L1 caches from an MPU core in a cycle. Experiments using several benchmark programs demonstrate that the STC architecture reduces the energy consumption of memory subsystems by 13% without any performance degradation compared to the best results obtained by previous approaches.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123336133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A CMOS linear preamplifier design for electret microphones 驻极体麦克风CMOS线性前置放大器设计
2008 International SoC Design Conference Pub Date : 2008-11-24 DOI: 10.1109/SOCDC.2008.4815673
Gil-Seop Park, S. Ryu
{"title":"A CMOS linear preamplifier design for electret microphones","authors":"Gil-Seop Park, S. Ryu","doi":"10.1109/SOCDC.2008.4815673","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815673","url":null,"abstract":"A gm-opamp-RC configured CMOS linear preamplifier for electret microphone is presented in this paper. The transconductance amplifier (gm-cell), as a V/I convertor at the input stage of the preamplifier, adopts a negative feedback loop at its input pair to enhance the linearity of the output current. Feedback loop improves the SFDR of the preamplifier by 9 dB. Simulated peak signal-to-noise and distortion ratio (SNDR) is 62 dB at 100 mVpp with 2 pF switching capacitor load at 2.56 MHz. The preamplifier operates under 1.8 V supply voltage and the total current consumption is 190 muA. It has been designed for a 0.18 mum CMOS technology.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117259951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Millimeter-wave CMOS power amplifiers in common-source MOSFETs 共源mosfet中的毫米波CMOS功率放大器
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815657
Sang-Hyun Hwang, Seong-Gwon Lee, Jong‐Wook Lee, Byung-sung Kim
{"title":"Millimeter-wave CMOS power amplifiers in common-source MOSFETs","authors":"Sang-Hyun Hwang, Seong-Gwon Lee, Jong‐Wook Lee, Byung-sung Kim","doi":"10.1109/SOCDC.2008.4815657","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815657","url":null,"abstract":"In this paper, CMOS millimeter-wave power amplifiers operating at Q-band (40 GHz) and Ka-band (27 GHz) are presented. The Q-band amplifier was designed using 0.13 mum standard CMOS process having 6 layers of copper metallization, and the amplifier resulted in a small-signal gain of 9.3 dB at 40 GHz when biased at IDS = 53 mA and VDS = 1.5 V. The Ka-band amplifier was design using 0.18 mum RF CMOS process. The amplifier showed a small-signal gain of 14.5 dB at 27 GHz when biased at IDS = 94 mA and VDS = 1.8 V. The results show the potential of CMOS millimeter-wave system-on-chip (SoC) at frequencies greater than 20 GHz.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115339677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A discussion on SRAM circuit design trend in deeper nano-meter era 深度纳米时代SRAM电路设计趋势探讨
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815598
H. Yamauchi
{"title":"A discussion on SRAM circuit design trend in deeper nano-meter era","authors":"H. Yamauchi","doi":"10.1109/SOCDC.2008.4815598","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815598","url":null,"abstract":"This paper describes the comparisons of area scaling trend of various SRAM margin-assist solutions for VT variability issues, which are based on efforts by not only the cell topology changes from 6 T to 8 T and 10 T but also incorporating multiple voltages supply for cell terminal biasing and timing sequence controls of read and write. The various solutions are analyzed in light of an impact of ever increasing VT variation (sigmaVT) on the required area overhead for each design solution, resulting in slowdown in the scaling pace. It has been found that 6 T will be allowed long reign even in 15 nm, if sigmaVT increasing pace is optimistically assumed, which sigmaVT can be suppressed to <70 mV even at 15 nm, thanks to EOT scaling for LSTP process, otherwise 10 T and 8 T with read modify write will be needed.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125181664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Discontinuous RC interconnect line analysis for accurate timing determination 断续RC互连线分析精确定时确定
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815707
Taehoon Kim, Youngdoo Song, Y. Eo
{"title":"Discontinuous RC interconnect line analysis for accurate timing determination","authors":"Taehoon Kim, Youngdoo Song, Y. Eo","doi":"10.1109/SOCDC.2008.4815707","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815707","url":null,"abstract":"In this research, discontinuous interconnect lines are modeled as a cascaded line composed of many uniform interconnect lines. The system functions of respective uniform interconnect lines are determined, followed by its time domain response. Since the time domain response expression is a transcendental form, the waveform expression is reconfigured as an approximated linear expression. The proposed model has less than 2% error in the delay estimation.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127042188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A heuristic method to reduce fault candidates for a speedy fault diagnosis 采用启发式方法减少故障候选项，实现快速故障诊断
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815607
Hyungjun Cho, Joohwan Lee, Sungho Kang
{"title":"A heuristic method to reduce fault candidates for a speedy fault diagnosis","authors":"Hyungjun Cho, Joohwan Lee, Sungho Kang","doi":"10.1109/SOCDC.2008.4815607","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815607","url":null,"abstract":"In this paper, we present a heuristic method to reduce fault candidates for an efficient fault diagnosis. This paper uses a matching algorithm for the exact fault diagnosis. But the time consumption of a fault diagnosis using the matching algorithm is huge. So, we present a new method to reduce the fault diagnosis time. The method to reduce the time consumption is separated into two different phases which are a pattern comparison and a back-tracing comparison in failing pattern. The proposed method reduces fault candidates by comparing failing patterns with good patterns during critical path tracing process and comparing back-tracing from non-erroneous POs with back-tracing erroneous POs. The proposed method increases the simulation speed than the conventional algorithms. And this method is also applicable to any other fault diagnosis algorithms. Experimental results on ISCAS'85 and ISCAS'89 benchmark circuits show that fault candidate lists are reduced than those of previous diagnosis methods.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115013674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new design method to reduce the power consumption in a flash-A/D converter 一种降低闪存A/D转换器功耗的新设计方法
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815669
Soon-Ik Cho, Soon-Kyung Choi, Suki Kim, K. Baek
{"title":"A new design method to reduce the power consumption in a flash-A/D converter","authors":"Soon-Ik Cho, Soon-Kyung Choi, Suki Kim, K. Baek","doi":"10.1109/SOCDC.2008.4815669","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815669","url":null,"abstract":"In this paper, we propose a new design method to control the clock duty ratio of a flash-A/D converter. Using this method, the power consumption of comparators in an A/D converter can be reduced drastically with very few additional circuits. Digital back-end including error-correction and encoding block also have more time to treat data from comparators due to being extended data length. Additionally, we can reduce the area of comparators and digital back-end. Simulation results show that the power consumption of a comparator using clock which has a duty ratio of 0.25 is more efficient by about 50% compared to a comparator which uses clock with a duty ratio of 0.5.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116231990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
R-less and C-less self-sampled ASK demodulator for lower ISM band applications 用于较低ISM频带应用的无r和无c自采样ASK解调器
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815627
Chi-Chun Huang, Chih-Lin Chen, Chua-Chin Wang
{"title":"R-less and C-less self-sampled ASK demodulator for lower ISM band applications","authors":"Chi-Chun Huang, Chih-Lin Chen, Chua-Chin Wang","doi":"10.1109/SOCDC.2008.4815627","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815627","url":null,"abstract":"An ASK demodulator with a high bandwidth for lower ISM band frequencies is presented. A total of 15 MOS transistors are used in the proposed design without using any passive element. It is very compact to be integrated in an SOC (system-on-chip) for wireless communication biomedical applications, particularly in biomedical implant. The proposed design with a low area cost and low power consumption is easily to be integrated in other mobile medical devices. The self-sampled loop with a MOS equivalent capacitor compensation mechanism enlarges the bandwidth, which is more than enough to be adopted in any application using lower ISM bands.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"42 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116396666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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