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Efficient construction of minimal Spanning Tree avoiding rectilinear directional obstacles 避免直线方向障碍的最小生成树的高效构造
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815606
Kyosun Kim, R. Karri
{"title":"Efficient construction of minimal Spanning Tree avoiding rectilinear directional obstacles","authors":"Kyosun Kim, R. Karri","doi":"10.1109/SOCDC.2008.4815606","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815606","url":null,"abstract":"Recently, the obstacle avoidance in the minimum spanning tree (MST) problem, which is one of the most important CAD problems, has been received a great deal of attention. In general, this obstacle avoiding MST (OAMST) can be efficiently found as a sub-graph of a spanning grap (OASG) which is constructed by connecting neighboring pins and obstacle corners. Unfortunately, its application was quite limited since obstacles were restricted to be rectangular, and prohibit wiring routes from passing through them in both horizontal and vertical dimensions. In this paper, the problem is extended so that the obstacles may have rectilinear shapes, and allow wiring routes passing through them either in the horizontal or vertical dimension. A finite state machine-based approach is proposed to recognize the complicated obstacle patterns, and precisely create edges that construct the OASG. Two algorithms from previous work have been modified to include this approach without increasing the computational complexity. The proposed approach and algorithm have been implemented and validated on a comprehensible set of nets that are sampled from an industrial strength system-on-chip design.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"14 24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132453666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient variable length decoding using N-bit code table for multi-format video applications
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815593
Seunghyun Cho, Moo-Kyung Jung, S. Park, N. Eum
{"title":"Efficient variable length decoding using N-bit code table for multi-format video applications","authors":"Seunghyun Cho, Moo-Kyung Jung, S. Park, N. Eum","doi":"10.1109/SOCDC.2008.4815593","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815593","url":null,"abstract":"In this paper, the method to generate and use a lookup table from a variable length codes (VLC) table, the so-called N-bit code table is described. The original VLC table is stored in a tree structure, and then transformed to the N-bit code table through the process presented on the paper. The proposed method can be applied to any VLC table regardless of the video formats. The implementation of the method accelerating a general RISC reduces the number of memory access from 48.3% up to 95.17% compared to the RISC without the implementation when applied to VLC tables of H.264/AVC.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"01 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130182785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Integrated current readout circuit and DMFET array for label-free detection of cancer marker 集成电流读出电路和DMFET阵列用于无标记癌症标志物检测
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815752
M. Im, Jae-Hyuk Ahn, Yang‐Kyu Choi
{"title":"Integrated current readout circuit and DMFET array for label-free detection of cancer marker","authors":"M. Im, Jae-Hyuk Ahn, Yang‐Kyu Choi","doi":"10.1109/SOCDC.2008.4815752","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815752","url":null,"abstract":"This paper describes a current readout platform designed for dielectric modulated field effect transistor (DMFET) arrays to detect a prostate cancer marker without labeling. A chip of 16 DMFET array has been fabricated as a biosensor cartridge. Standard 0.35 mum CMOS technology has been used to fabricate the readout circuit which includes a current integrator and a 10-bit single-slope analog-to-digital converter (ADC). The prostate cancer marker has been successfully detected by monitoring a change of DMFET current with aid of the fabricated readout circuitry.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115880351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An active-RC filter with variable bandwidth and channel-selectivity characteristics 具有可变带宽和信道选择性特性的有源rc滤波器
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815563
Youngchang Choi, Sangduk Yu, Kichang Jang, Jungsoo Choi, Jungeui Park, Wooju Jeong, Joongho Choi
{"title":"An active-RC filter with variable bandwidth and channel-selectivity characteristics","authors":"Youngchang Choi, Sangduk Yu, Kichang Jang, Jungsoo Choi, Jungeui Park, Wooju Jeong, Joongho Choi","doi":"10.1109/SOCDC.2008.4815563","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815563","url":null,"abstract":"This paper presents the design of an active-RC filter with variable bandwidth and channel-selectivity characteristics for wireless communication applications. The topology of this filter is the 5th-order low pass type. The 3-dB bandwidth is programmable at 10, 20 and 40 MHz. The filter is fabricated in a 0.13-mum CMOS technology and dissipates 13.2 mW for a supply voltage of 1.2 V.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"23 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131437565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High performance IPC hardware accelerator and communication network for MPSoCs 用于mpsoc的高性能IPC硬件加速器和通信网络
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815730
Moonmo Koo, S. Chae
{"title":"High performance IPC hardware accelerator and communication network for MPSoCs","authors":"Moonmo Koo, S. Chae","doi":"10.1109/SOCDC.2008.4815730","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815730","url":null,"abstract":"In this paper, we explain a configurable IPC module for multimedia MPSoCs, which was implemented in a MPW chip that include three ARM7 CPU cores. According to the test results for an M-JPEG and a H.264 decoder, its IPC synchronization overheads are not more than 1% when the synchronization period is about 5000 cycles.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130738652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-channel capacitive readout IC for MEMS inertial sensors 用于MEMS惯性传感器的多通道电容读出集成电路
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815731
W. Bahn, H. Ko, Cheolkyu Han, Sangyoon Lee, D. Jeong, D. Cho, Taedong Ahn, Kwangho Yoo
{"title":"Multi-channel capacitive readout IC for MEMS inertial sensors","authors":"W. Bahn, H. Ko, Cheolkyu Han, Sangyoon Lee, D. Jeong, D. Cho, Taedong Ahn, Kwangho Yoo","doi":"10.1109/SOCDC.2008.4815731","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815731","url":null,"abstract":"A multi-channel capacitive readout IC (integrated-circuit) for MEMS (microelectromechanical systems) inertial sensor is presented. A fully differential, chopper-stabilized SC (switched capacitor) 3-channel charge amplifier is designed. A digital demodulator and a decimator are used to prevent problems of conventional analog multipliers. Performance of the fabricated IC is evaluated with MEMS sensing elements.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"03 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130597957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance and wake-up schedule optimization of power gating design 电源门控设计的性能和唤醒计划优化
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815568
Ming-Chao Lee, Shih-Chieh Chang, Chun-Sung Su, E. Tsai
{"title":"Performance and wake-up schedule optimization of power gating design","authors":"Ming-Chao Lee, Shih-Chieh Chang, Chun-Sung Su, E. Tsai","doi":"10.1109/SOCDC.2008.4815568","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815568","url":null,"abstract":"Leakage power has become a major concern in mobile device and power gating is a very popular technique to reduce the leakage power. In this paper, we discuss two important optimization issues in power gating designs. One is the sizing problem of the sleep transistors which are the trade-off between the size and IR drop noise in the power gating designs. We also discuss the wake-up schedule optimization and propose efficient wake-up schedule for a power gating design. Our experimental results are very encouraging.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121570762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Low voltage analog digital converter using sigma-delta modulator 采用sigma-delta调制器的低压模拟数字转换器
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815745
Tae-Seong Jeong, W. Choi, Jun-Gi, C. Yoo
{"title":"Low voltage analog digital converter using sigma-delta modulator","authors":"Tae-Seong Jeong, W. Choi, Jun-Gi, C. Yoo","doi":"10.1109/SOCDC.2008.4815745","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815745","url":null,"abstract":"This paper proposes low voltage, low power discrete sigma-delta modulator for DVB-H. Full-feedforward structure and double sampling technique were used in order to achieve low voltage and wide bandwidth. To overcome the noise folding problem, generated when double sampling technique is applied, fully floating DAC is used. Simulated results of the modulator, designed in a 0.18 mum CMOS technology, achieves a 58 dB SNDR in a 4 MHz bandwidth and dissipates 8 mW from a 1.2 V supply.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123807971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Performance evaluation of Butterfly on-Chip Network for MPSoCs 用于mpsoc的蝶形片上网络的性能评价
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815631
M. Arjomand, H. Sarbazi-azad
{"title":"Performance evaluation of Butterfly on-Chip Network for MPSoCs","authors":"M. Arjomand, H. Sarbazi-azad","doi":"10.1109/SOCDC.2008.4815631","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815631","url":null,"abstract":"By Technology improvement, tens or hundreds of IP cores, operating complex functions with different frequencies, are mapped on-chip. This results in heterogeneous multiprocessor system-on-chip (MPSoC). The most MPSoC design challenges are due to infrastructure interconnect. Network-on-chip (NoC) with multiple constraints to be satisfied is a promising solution for these challenges. It has been shown that infrastructure topology, routing and switching schemes have great effects on overall interconnect performance under different synthesis and real life traffic patterns. In this paper, we evaluate Butterfly network with arbitrary extra stages as MPSoC infrastructure. Different routing and switching strategies are used for architectural consideration. Comparative analysis of results with common NoC infrastructures shows that in bandwidth requirement applications, Butterfly with extra stages and wormhole (and sometimes virtual cut through) switching can tolerate traffic, properly. As case studies, design space exploration including different topologies, routing and switching strategies for two video decoders are presented.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115040967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A design of full-CMOS VDSL2 receiver in 0.25μm CMOS process 基于0.25μm CMOS工艺的全CMOS VDSL2接收机设计
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815640
Young-Shin Kim, Younggun Pu, Tai-Young Kim, Hoohyun Cho, D. Ko, Kangyoon Lee, Tai-Hyung Kim, Joon-Beom Lee
{"title":"A design of full-CMOS VDSL2 receiver in 0.25μm CMOS process","authors":"Young-Shin Kim, Younggun Pu, Tai-Young Kim, Hoohyun Cho, D. Ko, Kangyoon Lee, Tai-Hyung Kim, Joon-Beom Lee","doi":"10.1109/SOCDC.2008.4815640","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815640","url":null,"abstract":"This paper presents a full-CMOS single-chip Receiver PHY IC for VDSL2 systems. In the receiver part, the low-pass filter, VGA, and ADC is designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. This chip is fabricated with 0.25 mum CMOS technology, and the die area is 5 mm times 5 mm. The power consumption is 250 mW at 2.5 V supply voltage in Rx mode.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122510081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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