用于mpsoc的高性能IPC硬件加速器和通信网络

2008 International SoC Design Conference Pub Date : 2008-11-01 DOI:10.1109/SOCDC.2008.4815730

Moonmo Koo, S. Chae

{"title":"用于mpsoc的高性能IPC硬件加速器和通信网络","authors":"Moonmo Koo, S. Chae","doi":"10.1109/SOCDC.2008.4815730","DOIUrl":null,"url":null,"abstract":"In this paper, we explain a configurable IPC module for multimedia MPSoCs, which was implemented in a MPW chip that include three ARM7 CPU cores. According to the test results for an M-JPEG and a H.264 decoder, its IPC synchronization overheads are not more than 1% when the synchronization period is about 5000 cycles.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"High performance IPC hardware accelerator and communication network for MPSoCs\",\"authors\":\"Moonmo Koo, S. Chae\",\"doi\":\"10.1109/SOCDC.2008.4815730\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we explain a configurable IPC module for multimedia MPSoCs, which was implemented in a MPW chip that include three ARM7 CPU cores. According to the test results for an M-JPEG and a H.264 decoder, its IPC synchronization overheads are not more than 1% when the synchronization period is about 5000 cycles.\",\"PeriodicalId\":405078,\"journal\":{\"name\":\"2008 International SoC Design Conference\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International SoC Design Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCDC.2008.4815730\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International SoC Design Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCDC.2008.4815730","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

在本文中，我们解释了多媒体mpsoc的可配置IPC模块，该模块在包含三个ARM7 CPU内核的MPW芯片上实现。根据M-JPEG和H.264解码器的测试结果，当同步周期约为5000个周期时，其IPC同步开销不大于1%。

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High performance IPC hardware accelerator and communication network for MPSoCs

In this paper, we explain a configurable IPC module for multimedia MPSoCs, which was implemented in a MPW chip that include three ARM7 CPU cores. According to the test results for an M-JPEG and a H.264 decoder, its IPC synchronization overheads are not more than 1% when the synchronization period is about 5000 cycles.

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2008 International SoC Design Conference

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