{"title":"Multimedia application extension processor(MAEP)","authors":"Sangkwon Na, Seungrok Jung, C. Kyung","doi":"10.1109/SOCDC.2008.4815748","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815748","url":null,"abstract":"We propose a multimedia application extension processor (MAEP) which supports diverse I/O interfaces and consumes low power. The MAEP embeds an H.264/AVC decoder to support real-time decoding and storage playback of H.264-coded bit-stream. Our H.264/AVC decoder, VHCORE, achieves 1.8 mW for CIF@30 fps real-time decoding. We adopt an extensible processor and extended SIMD instructions to accelerate audio CODEC application. Finally, we fabricate the MAEP in Samsung 0.18 um technology with an area of 12.54 mm2.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128881003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hybrid architecture of full-search block-matching motion estimation circuit for MPEG-4 encoder","authors":"Jaeoh Shim, Seonyoung Lee, Kyeongsoon Cho","doi":"10.1109/SOCDC.2008.4815613","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815613","url":null,"abstract":"This paper presents the hybrid architecture of full-search block-matching motion estimation circuit for MPEG-4 encoder. The proposed hybrid architecture requires smaller number of clock cycles and circuit resources compared to other approaches. In order to reduce the number of clock cycles, we use several techniques such as data reuse, pipelining and parallel structure. We reduce the circuit resources by the use of partial tree-structure. We described the RTL circuit in Verilog HDL and synthesized the gate-level crcuit using 130 nm standard cel library. The synthesized circuit is composed of 192,772 logic gates and can process 94 D1 (720 times 480) image frame per second.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127053399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power grid optimization with consideration of timing violation by IR drop","authors":"Y. Kawakami, M. Fukui, S. Tsukiyama","doi":"10.1109/SOCDC.2008.4815585","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815585","url":null,"abstract":"With the advent of super deep submicron age, the circuit performance is strongly impacted by the process variation. Power grid optimization which considers the timing error risk caused by the variation becomes very important for the stable and high-speed operation of the system. Most of conventional power grid optimization algorithms use the IR drop as their objective function. However, the real goal for optimizing the IR drop is eliminating the timing error risk by it. Thus, we propose a new approach which uses the ldquotiming error risk caused by the IR droprdquo as its direct objective function. The process variation is also considered in the timing model. The new optimization method obtains variation tolerant and high quality results efficiently.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132908425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation of efficient architecture of two-dimensional discrete wavelet transform","authors":"Jinook Song, I. Park","doi":"10.1109/SOCDC.2008.4815749","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815749","url":null,"abstract":"This paper presents a new architecture of 2-dimensional discrete wavelet transform for JPEG2000, and the architecture is verified by implementing on FPGA board. The tile-based processing is proposed which removes the transpose buffer effectively.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"70 Suppl4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133480521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Young-bea Park, Se-Ho Kim, Y. Yun, Kyu-Ho Park, K. Ahn, Kim Ki-jin, Kim Jin-Sup, Cho, Se-Hwan
{"title":"RF receiver chip set employing 0.13 μm CMOS technology for application to K-band commercial automotive radar system","authors":"Young-bea Park, Se-Ho Kim, Y. Yun, Kyu-Ho Park, K. Ahn, Kim Ki-jin, Kim Jin-Sup, Cho, Se-Hwan","doi":"10.1109/SOCDC.2008.4815705","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815705","url":null,"abstract":"A 24 GHz low-noise amplifier (LNA) and mixer for automotive radar applications was designed using a standard 0.13-mum CMOS technology. For mixer, single balanced resistive mixer was employed to suppress LO leakage signal on RF port. At 24 GHz, the mixer showed a conversion loss of -5.5 dB, an LO leakage suppression of -56.2 dBc on RF port, and 3rd input intercept point of 12 dBm. To achieve sufficient gain, this LNA is composed of three cascaded common-source stages. Source degeneration inductor was used to achieve low noise, and gate resistive matching was used to increase stability. The LNA showed a gain of 15.3 dB and a noise figure of 4.49 dB at 24 GHz, and it showed unconditional stability.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"18 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130098798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kwang-Il Oh, L. Kim, Kwang-il Park, Young-Hyun Jun, Kinam Kim
{"title":"Cancelation of a crosstalk induced noise in a DDR memory interface","authors":"Kwang-Il Oh, L. Kim, Kwang-il Park, Young-Hyun Jun, Kinam Kim","doi":"10.1109/SOCDC.2008.4815750","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815750","url":null,"abstract":"A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18mum CMOS process and operates at 5-Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The p-p jitter of output data is 52.82-ps.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116178527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hyun-Jun Yoon, M. Yang, YongJoon Kim, Youngkyu Park, Jaeseok Park, Sungho Kang
{"title":"An effective parallel ALPG using instruction unrolling for high speed memory testing","authors":"Hyun-Jun Yoon, M. Yang, YongJoon Kim, Youngkyu Park, Jaeseok Park, Sungho Kang","doi":"10.1109/SOCDC.2008.4815649","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815649","url":null,"abstract":"This paper presents the design and implementation of a new parallel Algorithmic Pattern Generator (ALPG) of Automatic Test Equipment (ATE) for the high speed memory testing. We implemented the Instruction Analyzer (IA) that unrolls the instructions using simple instructions. And, unrolled instruction memory is also implemented to reduce the delay of the IA. These implementations allow the ALPG to operate flexible algorithms at high speed. For high speed, we also designed the ALPG of multiple Pattern Generators (PG) with phase-shifting clocks. Therefore, the ALPG has expandability and operates at high speed with the high flexibility of the algorithms.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114983196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On-line learning based dynamic thermal management for multicore systems","authors":"Wonjin Kim, J. Song, Ki-Seok Chung","doi":"10.1109/SOCDC.2008.4815654","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815654","url":null,"abstract":"Power consumption of a high-end microprocessor increases very rapidly. High power consumption will lead to rapid increase in chip temperature as well. If temperature reaches beyond a certain level, chip operation becomes either slow or unreliable. Therefore various approaches for dynamic thermal management (DTM) have been proposed. In this paper, we propose a new application-oriented learning-based dynamic thermal management (LDTM) technique for a multi-core system. From repetitive executions of an application, we learn the thermal patterns of the chip, and we control the future temperature through DTM. When the predicted temperature may rise above a threshold value, we reduce the temperature by decreasing the operation frequency of the corresponding core. We implement our learning-based thermal management on an Intel's dual core system which is equipped with digital thermal sensors (DTS). The dynamic frequency scaling (DFS) is implemented to have three frequency steps on a Linux kernel. We carried out experiments using Phoronix Test Suite benchmarks for Linux. The peak temperature has been reduced by on average 7degC using our LDTM, and the overall average temperature reduced from 72degC to 65degC.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132247144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Readout integrated circuits involving pixel-level ADC for microbolometers","authors":"C. Hwang, H.C. Lee","doi":"10.1109/SOCDC.2008.4815754","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815754","url":null,"abstract":"Readout integrated circuits involving a pixel-level analog-to-digital converter (ADC) are studied for 320 times 240 microbolometer focal plane arrays (FPAs). Each 2times2 pixel shares an readout circuit, including an operational amplifier(op-Amp), an integration capacitor and a single slope ADC. This readout circuit is designed to achieve 35 times 35 mum2 pixel size in 0.35 mum 2-poly 3-metal CMOS technology.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134369286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multiprocessor SoC design framework on Tightly-Coupled Thread model","authors":"T. Isshiki, Dongju Li, H. Kunieda","doi":"10.1109/SOCDC.2008.4815572","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815572","url":null,"abstract":"To provide a practical solution to the challenging problems of MPSoC designs, we have proposed a new framework for MPSoC designs which we call the tightly-coupled thread (TCT) model. Our TCT model provides a drastically simple programming model on C language which allows designers to specify system partitioning directly on the reference C code without having to deal with the time-consuming task of modeling the interactions between partitioned concurrent processes. Our TCT compiler handles automatic insertion of inter-processor communications and generates the concurrent executable model which can model a wide variety of parallel processing styles such as functional pipelining and task parallelism as well as their combinations. Our TCT trace scheduler is used to evaluate the system performance and characteristics such as execution time and communication bandwidth. Our TCT framework was also verified on a prototype MPSoC where a custom-designed processor array consisting of 6 processing elements was embedded inside the AMBA-based SoC with a very efficient processor communication interconnect which only require 2 to 6 setup cycles and 4-byte/cycle burst transfer.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134438333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}