2008 International SoC Design Conference最新文献_第8页

LTR: A low-overhead and reliable routing algorithm for network on chips LTR:一种低开销、可靠的芯片网络路由算法

2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815590

A. Patooghy, S. Miremadi

引用次数: 15

Design of memory controller Design of general purpose memory controller 通用存储控制器的设计

2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815739

Park Soo Il, Song Jae Yeol, Park Seok Hwi, J. Hoon

引用次数: 2

Design of voice guiding system using serial connection technique of speakers 基于扬声器串行连接技术的语音引导系统设计

2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815695

Jisung Byun, Sunyong Lee, Teawan Kim, J. Park, Yunmo Chung, Moonvin Song, Ohkyun Kwon

引用次数: 0

On-chip active RF tracking filter with 60dB 3rd-order harmonic rejection for digital TV tuners 用于数字电视调谐器的60dB三阶谐波抑制片上有源射频跟踪滤波器

2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815658

Yang Sun, Jeong-Seon Lee, Sang-Gug Lee

{"title":"On-chip active RF tracking filter with 60dB 3rd-order harmonic rejection for digital TV tuners","authors":"Yang Sun, Jeong-Seon Lee, Sang-Gug Lee","doi":"10.1109/SOCDC.2008.4815658","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815658","url":null,"abstract":"A new structure of RF tracking filter to solve the linearity and harmonic mixing problem in DTV (digital TV) tuner is proposed in this paper. The proposed structure composed of two filters: harmonic rejection tracking filter (HRTF) and RF tracking filter (RFTF). They are activated / deactivated by complementary digital control switches. HRTF works in the frequency range 48~287 MHz. It can reject not only 3 rd-order harmonic by more than 60 dB but also unwanted channel signal from 5 to 15 dB. The RFTF can reject unwanted signal from 287~860 MHz. The proposed structure can realize pre-band selection function in the tuner front-end and covers a wide frequency range from 48-860 MHz. The center frequency and the bandwidth of both filters can be tuned by adopting the proposed tuning method. Also, the proposed structure can be implemented without any off-chip component. Simulation results show the tunable ability of the center frequency from 48 to 860 MHz, and the bandwidth from 8~20 MHz. These features are obtained drawing 19.8 mA (7.2 mA from RFTF, 12.6 mA from HRTF) current from a 1.2-V supply in a standard 0.13 um CMOS technology.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125010238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Stability enhancement techniques for nanoscale SRAM circuits: A comparison 纳米级SRAM电路稳定性增强技术:比较

2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815586

S. Tawfik, V. Kursun

{"title":"Stability enhancement techniques for nanoscale SRAM circuits: A comparison","authors":"S. Tawfik, V. Kursun","doi":"10.1109/SOCDC.2008.4815586","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815586","url":null,"abstract":"Four circuit techniques for high data stability and low leakage power consumption in static CMOS memory circuits are compared in this paper. The techniques that provide the highest data stability, the lowest leakage power consumption, and the smallest memory cell area are identified. The first circuit technique employs a dynamic voltage swing wordline driver to control the operation of the standard six-transistor (6 T) memory cells. The wordline voltage swing is dynamically tuned during read and write operations in order to simultaneously enhance the read stability and the write margin without increasing the size of the transistors in the SRAM cell. The other three circuit techniques tackle the data stability challenge by modifying the memory cell circuit structure. A nine-transistor (9 T), an eighttransistor (8 T), and a dual-threshold-voltage (dual-Vt) seven-transistor (7 T) SRAM circuit are considered in this paper. The data storage nodes are isolated from the bitlines with these techniques, thereby significantly enhancing the read stability as compared to the standard 6 T SRAM circuits. Among the evaluated memory circuits, the 9 T and the 8 T SRAM cells provide the highest data stability during a read operation. The read stability of the 9 T and the 8 T SRAM cells is 80% higher as compared to a standard 6T SRAM cell sized for data stability (with beta = 3) in a 65 nm CMOS technology. Alternatively, the dynamic wordline voltage swing technique offers the smallest area and the dual-Vt 7 T SRAM cell consumes the lowest leakage power among the evaluated memory cells.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125477748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Digital integrated circuit design for system-on-glass 玻璃上系统的数字集成电路设计

2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815600

K. Ikai, Jinmyoung Kim, M. Ikeda, K. Asada

引用次数: 9

On modeling and sensitivity of via count in SOC physical implementation SOC物理实现中通孔数的建模与灵敏度研究

2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815589

Kwangok Jeong, A. Kahng, Hailong Yao

引用次数: 3

Design of 24 bit DSP for audio algorithms 设计24位DSP音频算法

2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815724

C. Ryu, Seungeon Hwang, Ju Sung Park

引用次数: 9

Low voltage time based CMOS active pixel sensor 低电压时基CMOS有源像素传感器

2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815582

Kunhee Cho, Dongmyung Lee, G. Han

引用次数: 1

1.5 MHz, 300 mA step-down switching regulator 1.5 MHz, 300 mA降压开关稳压器

2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815744

Dongsuk Lee, Hyunseok Nam, Youngkook Ahn, J. Roh

引用次数: 1