On modeling and sensitivity of via count in SOC physical implementation

Abstract

As VLSI technology nodes scale down, via defects are becoming a major yield concern. Thus, via estimation modeling is becoming more important for yield analysis. In this paper, the recent via distribution model of is revisited and analyzed, and possible inaccuracies and deficiencies are pointed out and experimentally verified. Then, a new taxonomy of via modeling approaches is presented, including analytical, netlist-based, and placement-based approaches. We focus on placement-based via estimation, and propose and validate a new model using real industry chips and public-domain testcases. Experimental results show that our via modeling approach is more accurate than the previous via distribution model.