Performance evaluation of Butterfly on-Chip Network for MPSoCs

Abstract

By Technology improvement, tens or hundreds of IP cores, operating complex functions with different frequencies, are mapped on-chip. This results in heterogeneous multiprocessor system-on-chip (MPSoC). The most MPSoC design challenges are due to infrastructure interconnect. Network-on-chip (NoC) with multiple constraints to be satisfied is a promising solution for these challenges. It has been shown that infrastructure topology, routing and switching schemes have great effects on overall interconnect performance under different synthesis and real life traffic patterns. In this paper, we evaluate Butterfly network with arbitrary extra stages as MPSoC infrastructure. Different routing and switching strategies are used for architectural consideration. Comparative analysis of results with common NoC infrastructures shows that in bandwidth requirement applications, Butterfly with extra stages and wormhole (and sometimes virtual cut through) switching can tolerate traffic, properly. As case studies, design space exploration including different topologies, routing and switching strategies for two video decoders are presented.