Heesauk Jhon, Hakchul Jung, M. Koo, Hyungcheol Shin
{"title":"一种用于ism波段应用的并发双频CMOS低噪声放大器","authors":"Heesauk Jhon, Hakchul Jung, M. Koo, Hyungcheol Shin","doi":"10.1109/SOCDC.2008.4815733","DOIUrl":null,"url":null,"abstract":"A dual-band CMOS low-noise amplifier (LNA) for ISM-band application is reported. For low power and dual band operation, the designed LNA adopts a positive-feedback LC-ladder network. Moreover, for cost effective approach, the LNA has been fabricated using a 0.18-mum mixed-signal CMOS process. The implemented LNA shows gain of 8.3 dB and 11.2 dB, and noise figure (NF) of 6.1 dB and 6.6 dB at 19 GHz and 25 GHz, respectively. The proposed LNA exhibits 8.1 mW power consumption from 0.8 V supply and the active chip area including pad is about 720 times 460 mum2.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A concurrent dual-band CMOS low-noise amplifier for ISM-band application\",\"authors\":\"Heesauk Jhon, Hakchul Jung, M. Koo, Hyungcheol Shin\",\"doi\":\"10.1109/SOCDC.2008.4815733\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A dual-band CMOS low-noise amplifier (LNA) for ISM-band application is reported. For low power and dual band operation, the designed LNA adopts a positive-feedback LC-ladder network. Moreover, for cost effective approach, the LNA has been fabricated using a 0.18-mum mixed-signal CMOS process. The implemented LNA shows gain of 8.3 dB and 11.2 dB, and noise figure (NF) of 6.1 dB and 6.6 dB at 19 GHz and 25 GHz, respectively. The proposed LNA exhibits 8.1 mW power consumption from 0.8 V supply and the active chip area including pad is about 720 times 460 mum2.\",\"PeriodicalId\":405078,\"journal\":{\"name\":\"2008 International SoC Design Conference\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International SoC Design Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCDC.2008.4815733\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International SoC Design Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCDC.2008.4815733","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A concurrent dual-band CMOS low-noise amplifier for ISM-band application
A dual-band CMOS low-noise amplifier (LNA) for ISM-band application is reported. For low power and dual band operation, the designed LNA adopts a positive-feedback LC-ladder network. Moreover, for cost effective approach, the LNA has been fabricated using a 0.18-mum mixed-signal CMOS process. The implemented LNA shows gain of 8.3 dB and 11.2 dB, and noise figure (NF) of 6.1 dB and 6.6 dB at 19 GHz and 25 GHz, respectively. The proposed LNA exhibits 8.1 mW power consumption from 0.8 V supply and the active chip area including pad is about 720 times 460 mum2.