A concurrent dual-band CMOS low-noise amplifier for ISM-band application

Heesauk Jhon, Hakchul Jung, M. Koo, Hyungcheol Shin
{"title":"A concurrent dual-band CMOS low-noise amplifier for ISM-band application","authors":"Heesauk Jhon, Hakchul Jung, M. Koo, Hyungcheol Shin","doi":"10.1109/SOCDC.2008.4815733","DOIUrl":null,"url":null,"abstract":"A dual-band CMOS low-noise amplifier (LNA) for ISM-band application is reported. For low power and dual band operation, the designed LNA adopts a positive-feedback LC-ladder network. Moreover, for cost effective approach, the LNA has been fabricated using a 0.18-mum mixed-signal CMOS process. The implemented LNA shows gain of 8.3 dB and 11.2 dB, and noise figure (NF) of 6.1 dB and 6.6 dB at 19 GHz and 25 GHz, respectively. The proposed LNA exhibits 8.1 mW power consumption from 0.8 V supply and the active chip area including pad is about 720 times 460 mum2.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International SoC Design Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCDC.2008.4815733","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

Abstract

A dual-band CMOS low-noise amplifier (LNA) for ISM-band application is reported. For low power and dual band operation, the designed LNA adopts a positive-feedback LC-ladder network. Moreover, for cost effective approach, the LNA has been fabricated using a 0.18-mum mixed-signal CMOS process. The implemented LNA shows gain of 8.3 dB and 11.2 dB, and noise figure (NF) of 6.1 dB and 6.6 dB at 19 GHz and 25 GHz, respectively. The proposed LNA exhibits 8.1 mW power consumption from 0.8 V supply and the active chip area including pad is about 720 times 460 mum2.
一种用于ism波段应用的并发双频CMOS低噪声放大器
报道了一种适用于ism波段的双频CMOS低噪声放大器(LNA)。为了实现低功耗和双频工作,所设计的LNA采用正反馈lc阶梯网络。此外,为了提高成本效益,LNA采用0.18 μ m混合信号CMOS工艺制造。所实现的LNA在19 GHz和25 GHz频段的增益分别为8.3 dB和11.2 dB,噪声系数(NF)分别为6.1 dB和6.6 dB。提出的LNA在0.8 V电源下功耗为8.1 mW,包括衬垫在内的有源芯片面积约为720乘以460 mum2。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信