Byungill Kim, Daeyun Kim, Jooho Hwang, Junho Moon, Minkyu Song
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引用次数: 5
摘要
本文设计了一种12位80 MSPS的1.8 V CMOS模数转换器(ADC)。该ADC的结构是基于双折叠和插值结构的折叠ADC。介绍了一种用于高分辨率、高速ADC的均匀折叠电路技术。此外，还提出了一种新型的自动开关编码器。该芯片采用0.18 um 1-聚6-金属CMOS技术制造。在1.8 V电源下，有效面积为1.6 mm2，功率为195 mw。DNL和INL分别在plusmn4/plusmn4LSB范围内。当Fin=1MHz, Fs= 80mhz时，SNDR的测量结果为46 dB。
In this paper, a CMOS analog-to-digital converter (ADC) with a 12-bit 80 MSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a folding ADC with a double folding and interpolating structure. An even folding circuit technique for the high resolution and high speed ADC are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18 um 1-poly 6-metal CMOS technology. The active area is 1.6 mm2 and 195 mw at 1.8 V power supply. The DNL and INL are within plusmn4/plusmn4LSB, respectively. The measured result of SNDR is 46 dB, when Fin=1MHz at Fs=80 MHz.
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