A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort

Abstract

This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7 Gbps and 1.62 Gbps for DisplayPort sink device. This CDR uses the half-rate linear phase detector (PD). A voltage-controlled oscillator (VCO) is proposed to change the operating frequency of half-rate clock with a ldquoModerdquo switch control. This work is implemented 0.18 mum CMOS process. The device exhibits peak-to-peak jitters of 12 ps and 14 ps in the recovered clock with random data inputs. The power dissipation is 81 mW from a 1.8 V supply.