{"title":"2.7Gbps和1.62Gbps双模时钟和数据恢复DisplayPort","authors":"Seungwon Lee, Jae-Wook Yoo, Jin-Ku Kang","doi":"10.1109/SOCDC.2008.4815672","DOIUrl":null,"url":null,"abstract":"This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7 Gbps and 1.62 Gbps for DisplayPort sink device. This CDR uses the half-rate linear phase detector (PD). A voltage-controlled oscillator (VCO) is proposed to change the operating frequency of half-rate clock with a ldquoModerdquo switch control. This work is implemented 0.18 mum CMOS process. The device exhibits peak-to-peak jitters of 12 ps and 14 ps in the recovered clock with random data inputs. The power dissipation is 81 mW from a 1.8 V supply.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort\",\"authors\":\"Seungwon Lee, Jae-Wook Yoo, Jin-Ku Kang\",\"doi\":\"10.1109/SOCDC.2008.4815672\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7 Gbps and 1.62 Gbps for DisplayPort sink device. This CDR uses the half-rate linear phase detector (PD). A voltage-controlled oscillator (VCO) is proposed to change the operating frequency of half-rate clock with a ldquoModerdquo switch control. This work is implemented 0.18 mum CMOS process. The device exhibits peak-to-peak jitters of 12 ps and 14 ps in the recovered clock with random data inputs. The power dissipation is 81 mW from a 1.8 V supply.\",\"PeriodicalId\":405078,\"journal\":{\"name\":\"2008 International SoC Design Conference\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International SoC Design Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCDC.2008.4815672\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International SoC Design Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCDC.2008.4815672","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
本文介绍了一种支持2.7 Gbps和1.62 Gbps双数据速率的时钟和数据恢复(CDR)电路。该CDR采用半速率线性鉴相器(PD)。提出了一种压控振荡器(VCO)，通过ldquoModerdquo开关控制来改变半速率时钟的工作频率。本工作实现了0.18 μ m CMOS工艺。该器件在随机数据输入的恢复时钟中显示出12ps和14ps的峰对峰抖动。1.8 V电源的功耗为81 mW。
A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort
This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7 Gbps and 1.62 Gbps for DisplayPort sink device. This CDR uses the half-rate linear phase detector (PD). A voltage-controlled oscillator (VCO) is proposed to change the operating frequency of half-rate clock with a ldquoModerdquo switch control. This work is implemented 0.18 mum CMOS process. The device exhibits peak-to-peak jitters of 12 ps and 14 ps in the recovered clock with random data inputs. The power dissipation is 81 mW from a 1.8 V supply.
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