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an optimized rendering algorithm for hardware implementation of openVG 2D vector graphics openVG二维矢量图形硬件实现的优化渲染算法
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815641
Kilhyung Cha, Daewoong Kim, S. Chae
{"title":"an optimized rendering algorithm for hardware implementation of openVG 2D vector graphics","authors":"Kilhyung Cha, Daewoong Kim, S. Chae","doi":"10.1109/SOCDC.2008.4815641","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815641","url":null,"abstract":"An optimized rendering algorithm of the OpenVG 2D vector graphics for hardware implementation is presented in this paper. In the rendering algorithm we adopted a hybrid of raster and vector rendering, which uses vector rendering only within each scanline, to reduce both the number of external memory accesses and the computational complexity. We implemented a hardware accelerator with the proposed algorithm. Experimental results show that our hardware accelerator can handle 11.8 fps of Tiger image for a QVGA panel at the operating clock frequency of 100 MHz.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131416757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The development of an energy-awared mobile 3D graphics SoC with real-time performance/energy monitoring and control 具有实时性能/能量监测和控制的能量感知移动3D图形SoC的开发
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815615
Liang-Bi Chen, Tsung-Yu Ho, Ing-Jer Huang, Yun-Nan Chang, S.W. Haga, Jin-Hua Hong, Shen-Fu Hsaio, Shiann-Rong Kuang, Ko-Chi Kuo, Chung-Nan Lee
{"title":"The development of an energy-awared mobile 3D graphics SoC with real-time performance/energy monitoring and control","authors":"Liang-Bi Chen, Tsung-Yu Ho, Ing-Jer Huang, Yun-Nan Chang, S.W. Haga, Jin-Hua Hong, Shen-Fu Hsaio, Shiann-Rong Kuang, Ko-Chi Kuo, Chung-Nan Lee","doi":"10.1109/SOCDC.2008.4815615","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815615","url":null,"abstract":"Portable mobile computing and communication applications demand low-power and low-energy with high performance. These competing demands drive SoC development. Especially, 3D graphics-intensive applications are predicted to become widely available on a variety of portable mobile devices ranging from laptops to PDAs to mobile phones. Such 3D graphics coprocessors were originally developed for home computers and game consoles, which use steady power supplies. But a portable mobile device has a limited battery life, which needs to be prolonged as much as possible. Consequently, low power design is the most important segment in order to become competitively portable mobile consumer electronics. We are developing a high-performance, low-power, 3D-graphics SoC to meet such requirements. This paper introduces our developing energy-awared mobile 3D graphics SoC and its real-time performance/energy monitoring and control.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131603585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Speeding up SoC virtual platform simulation by data-dependency aware virtual synchronization 基于数据依赖感知的虚拟同步加速SoC虚拟平台仿真
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815621
Kuen-Huei Lin, S. Cai, Chung-Yang Huang
{"title":"Speeding up SoC virtual platform simulation by data-dependency aware virtual synchronization","authors":"Kuen-Huei Lin, S. Cai, Chung-Yang Huang","doi":"10.1109/SOCDC.2008.4815621","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815621","url":null,"abstract":"This paper presents a novel simulation technique for SoC virtual platforms at transaction level to achieve million-instructions-per-second (MIPS) level of simulation speed, while retaining accurate and detailed cycle information for system explorations. We first apply virtual synchronization concept to our simulation algorithm and then apply a novel data-dependency aware concept to determine precise synchronization points in simulation. Our experimental result shows that comparing to the traditional cycle-accurate TLM simulation, our approach is about 44 times faster with the simulation speed around 3.66 MPIS.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115616890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Design of On-Chip Debug System for embedded processor 嵌入式处理器片上调试系统的设计
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815725
Hyungbae Park, Jingzhe Xu, Jusung Park, Jung-Hoon Ji, G. Woo
{"title":"Design of On-Chip Debug System for embedded processor","authors":"Hyungbae Park, Jingzhe Xu, Jusung Park, Jung-Hoon Ji, G. Woo","doi":"10.1109/SOCDC.2008.4815725","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815725","url":null,"abstract":"In this paper, we introduce on-chip debug system (OCDS) which supports symbolic debugging at c-level using OCD integrated Debug-logic into target processor. The OCDS consist of SW debugger that supports a functionality of symbolic debugging, OCD (on-chip debugger) serving as a debugger of internal state of target processor, and Interface & Control block interfacing SW debugger and OCD. After OCD block is interfaced with 32 bit RISC processor core and then implemented with FPGA, OCD is connected by Interface & Control block, and SW debugger. The verification of the design is carried out through device recognition, carrying-out instructions of JTAG(joint test action group), reading and writing the internal registers of the processor and memory, and checking the emulation functions such as setting break-points and watch points.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114821516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design of a motion compensation unit for H.264 decoder using 2-dimensional circular register files 基于二维圆形寄存器文件的H.264解码器运动补偿单元设计
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815696
Chanho Lee, Yong-Hoon Yu
{"title":"Design of a motion compensation unit for H.264 decoder using 2-dimensional circular register files","authors":"Chanho Lee, Yong-Hoon Yu","doi":"10.1109/SOCDC.2008.4815696","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815696","url":null,"abstract":"H.264 video coding standard is widely used due to the high compression rate and quality. The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation and management of the reference pixels. The reference pixels read from external memory and efficient memory management for data reuse is necessary. We propose the architecture of a motion compensation for H.264 decoders. It is composed of 2-dimensional circular register files, a motion vector predictor and interpolators with dual-channel pipelined processing elements. The processing elements can interpolate integer-, half- and quarter-pixel data. The 2-dimensional circular register files reuse reference pixel data as much as possible, and feed reference pixel data to interpolators without any latency and complex logic circuits. The motion compensation unit has dual processing pipelines for luminance and chroma data. We design a motion compensation unit for the baseline profile using Verilog-HDL.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"30 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115861902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
ILP based data parallel multi-task mapping/scheduling technique for MPSoC 基于ILP的MPSoC数据并行多任务映射/调度技术
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815591
Hoeseok Yang, S. Ha
{"title":"ILP based data parallel multi-task mapping/scheduling technique for MPSoC","authors":"Hoeseok Yang, S. Ha","doi":"10.1109/SOCDC.2008.4815591","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815591","url":null,"abstract":"In this paper, we propose a multi-task mapping/scheduling technique for heterogeneous and scalable MPSoC. To cope with ever increasing computational demand and to utilize large number of cores effectively, the proposed technique considers data parallelism as well as task parallelism. The solution is based on ILP (Integer Linear Programming) and its effectiveness is proven by experiments with real-life examples.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123060645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
A 26mW dual-mode RF receiver for GPS/Galileo with L1/L1F and L5/E5a bands 26mW双模射频接收机，用于GPS/Galileo, L1/L1F和L5/E5a频段
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815662
Yo-Sup Moon, Sanghyun Cha, G. Kim, K. Park, Sunjun Ko, Heonchul Park, Jubong Park, Jaeheon Lee
{"title":"A 26mW dual-mode RF receiver for GPS/Galileo with L1/L1F and L5/E5a bands","authors":"Yo-Sup Moon, Sanghyun Cha, G. Kim, K. Park, Sunjun Ko, Heonchul Park, Jubong Park, Jaeheon Lee","doi":"10.1109/SOCDC.2008.4815662","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815662","url":null,"abstract":"A CMOS RF receiver for L1/L1F and L5/E5a dual-band GPS/Galileo system is designed in a 0.13 m standard CMOS process. It can be fully integrated in System-on-Chip (SoC) solution for GPS and Galileo. The receiver includes a low-noise amplifier (LNA), down-conversion mixers, channel selection filters (CSF), 2-bit analog-to-digital converters (ADC) and the full phase-locked-loop (PLL) synthesizers as well as on-chip voltage-controlled-oscillator (VCO). The dual-band LNA achieves a noise figure (NF) of 2.2 dB and a gain of 16 dB for each band. The PLL exhibits phase noise of -90 dBc/Hz at 100 kHz offset frequency. The receiver consumes 26 mW for a supply voltage of 1.2 V while occupying a 3times3.8 mm2 die area including ESD I/Q pads.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124844288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A generalized framework for energy savings in real-time multiprocessor systems 实时多处理器系统节能的通用框架
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815570
Gang Zeng, T. Yokoyama, H. Tomiyama, H. Takada, T. Ishihara
{"title":"A generalized framework for energy savings in real-time multiprocessor systems","authors":"Gang Zeng, T. Yokoyama, H. Tomiyama, H. Takada, T. Ishihara","doi":"10.1109/SOCDC.2008.4815570","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815570","url":null,"abstract":"A generalized dynamic energy performance scaling (DEPS) framework is proposed for exploring application-specific energy-saving potential in multiprocessor systems. This software-centric framework takes advantage of possible power control mechanisms to trade off performance for energy savings. Three existing technologies, i.e., dynamic hardware resource configuration (DHRC), dynamic voltage frequency scaling (DVFS), and dynamic power management (DPM), have been employed in this framework to achieve the maximal energy savings. The problem of determining the optimal task allocation and DEPS configurations is formulated as an integer linear programming (ILP) problem. Several practical issues such as how to reduce measurement and computation time and how to reduce the configuration overhead are also addressed. The effectiveness of DEPS is validated through a case study.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125775728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of high energy efficiency 32bit processing unit using instruction-levels data gating and dynamic voltage scaling techniques 利用指令级数据门控和动态电压缩放技术设计高能效32位处理单元
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815686
Yil Suk Yang, T. Roh, Soon-il Yeo, W.H. Kwon, Jongdae Kim
{"title":"Design of high energy efficiency 32bit processing unit using instruction-levels data gating and dynamic voltage scaling techniques","authors":"Yil Suk Yang, T. Roh, Soon-il Yeo, W.H. Kwon, Jongdae Kim","doi":"10.1109/SOCDC.2008.4815686","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815686","url":null,"abstract":"This paper describes design and circuit simulation of the high energy efficiency 32bit processing unit (PU) using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating and DVS technique. We can control activation and switching activity of the function units using the proposed data gating technique and we can control powers of the function units using the proposed DVS technique. We simulated the power and circuit simulation for running test program using Spectra with layout extraction data which does not include PAD. We selected the optimum reduced power supply to 0.667 times of the supplied power supply in this paper. The energy efficiency of the proposed 32bit processing unit using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32bit processing unit without using instruction-levels data gating and DVS techniques. The energy efficiency of the proposed instruction-level DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system but a hardware implementation is very easy. The designed high energy efficiency 32bit processing unit can utilize as the coprocessor processing massive data at high speed.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129688459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Communication modeling for system-level design 用于系统级设计的通信建模
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815592
A. Kahng, K. Samadi
{"title":"Communication modeling for system-level design","authors":"A. Kahng, K. Samadi","doi":"10.1109/SOCDC.2008.4815592","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815592","url":null,"abstract":"Multiprocessor systems-on-chip (MPSoCs) are emerging as a popular SoC design platform. However, major challenges arise from nonscaling global wire delay and from the reuse of intellectual properties (IPs) from different vendors to meet tight time-to-market constraints. Designing the appropriate communication fabrics for such heterogeneous systems becomes a challenging task. In this paper, we present accurate delay, power, and area models for bus-based and packet-switched communication architectures. We also integrate our models into the COSI-OCC system-level communication synthesis tool and show that the more accurate modeling significantly affects optimal/achievable architectures that are synthesized by the system-level tool. Finally, this paper reviews our relevant contributions in.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129429623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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