A 26mW dual-mode RF receiver for GPS/Galileo with L1/L1F and L5/E5a bands

Yo-Sup Moon, Sanghyun Cha, G. Kim, K. Park, Sunjun Ko, Heonchul Park, Jubong Park, Jaeheon Lee
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引用次数: 22

Abstract

A CMOS RF receiver for L1/L1F and L5/E5a dual-band GPS/Galileo system is designed in a 0.13 m standard CMOS process. It can be fully integrated in System-on-Chip (SoC) solution for GPS and Galileo. The receiver includes a low-noise amplifier (LNA), down-conversion mixers, channel selection filters (CSF), 2-bit analog-to-digital converters (ADC) and the full phase-locked-loop (PLL) synthesizers as well as on-chip voltage-controlled-oscillator (VCO). The dual-band LNA achieves a noise figure (NF) of 2.2 dB and a gain of 16 dB for each band. The PLL exhibits phase noise of -90 dBc/Hz at 100 kHz offset frequency. The receiver consumes 26 mW for a supply voltage of 1.2 V while occupying a 3times3.8 mm2 die area including ESD I/Q pads.
26mW双模射频接收机,用于GPS/Galileo, L1/L1F和L5/E5a频段
设计了一种适用于L1/L1F和L5/E5a双频GPS/Galileo系统的CMOS射频接收机,采用0.13 m标准CMOS工艺。它可以完全集成在GPS和伽利略系统的片上系统(SoC)解决方案中。该接收器包括低噪声放大器(LNA)、下变频混频器、通道选择滤波器(CSF)、2位模数转换器(ADC)和全锁相环(PLL)合成器以及片上压控振荡器(VCO)。双频LNA每个频段的噪声系数(NF)为2.2 dB,增益为16 dB。锁相环在100 kHz偏置频率下的相位噪声为-90 dBc/Hz。在1.2 V的电源电压下,接收器消耗26 mW,同时占用3倍3.8 mm2的芯片面积,包括ESD I/Q焊盘。
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