Yo-Sup Moon, Sanghyun Cha, G. Kim, K. Park, Sunjun Ko, Heonchul Park, Jubong Park, Jaeheon Lee
{"title":"26mW双模射频接收机,用于GPS/Galileo, L1/L1F和L5/E5a频段","authors":"Yo-Sup Moon, Sanghyun Cha, G. Kim, K. Park, Sunjun Ko, Heonchul Park, Jubong Park, Jaeheon Lee","doi":"10.1109/SOCDC.2008.4815662","DOIUrl":null,"url":null,"abstract":"A CMOS RF receiver for L1/L1F and L5/E5a dual-band GPS/Galileo system is designed in a 0.13 m standard CMOS process. It can be fully integrated in System-on-Chip (SoC) solution for GPS and Galileo. The receiver includes a low-noise amplifier (LNA), down-conversion mixers, channel selection filters (CSF), 2-bit analog-to-digital converters (ADC) and the full phase-locked-loop (PLL) synthesizers as well as on-chip voltage-controlled-oscillator (VCO). The dual-band LNA achieves a noise figure (NF) of 2.2 dB and a gain of 16 dB for each band. The PLL exhibits phase noise of -90 dBc/Hz at 100 kHz offset frequency. The receiver consumes 26 mW for a supply voltage of 1.2 V while occupying a 3times3.8 mm2 die area including ESD I/Q pads.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"A 26mW dual-mode RF receiver for GPS/Galileo with L1/L1F and L5/E5a bands\",\"authors\":\"Yo-Sup Moon, Sanghyun Cha, G. Kim, K. Park, Sunjun Ko, Heonchul Park, Jubong Park, Jaeheon Lee\",\"doi\":\"10.1109/SOCDC.2008.4815662\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CMOS RF receiver for L1/L1F and L5/E5a dual-band GPS/Galileo system is designed in a 0.13 m standard CMOS process. It can be fully integrated in System-on-Chip (SoC) solution for GPS and Galileo. The receiver includes a low-noise amplifier (LNA), down-conversion mixers, channel selection filters (CSF), 2-bit analog-to-digital converters (ADC) and the full phase-locked-loop (PLL) synthesizers as well as on-chip voltage-controlled-oscillator (VCO). The dual-band LNA achieves a noise figure (NF) of 2.2 dB and a gain of 16 dB for each band. The PLL exhibits phase noise of -90 dBc/Hz at 100 kHz offset frequency. The receiver consumes 26 mW for a supply voltage of 1.2 V while occupying a 3times3.8 mm2 die area including ESD I/Q pads.\",\"PeriodicalId\":405078,\"journal\":{\"name\":\"2008 International SoC Design Conference\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International SoC Design Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCDC.2008.4815662\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International SoC Design Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCDC.2008.4815662","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 26mW dual-mode RF receiver for GPS/Galileo with L1/L1F and L5/E5a bands
A CMOS RF receiver for L1/L1F and L5/E5a dual-band GPS/Galileo system is designed in a 0.13 m standard CMOS process. It can be fully integrated in System-on-Chip (SoC) solution for GPS and Galileo. The receiver includes a low-noise amplifier (LNA), down-conversion mixers, channel selection filters (CSF), 2-bit analog-to-digital converters (ADC) and the full phase-locked-loop (PLL) synthesizers as well as on-chip voltage-controlled-oscillator (VCO). The dual-band LNA achieves a noise figure (NF) of 2.2 dB and a gain of 16 dB for each band. The PLL exhibits phase noise of -90 dBc/Hz at 100 kHz offset frequency. The receiver consumes 26 mW for a supply voltage of 1.2 V while occupying a 3times3.8 mm2 die area including ESD I/Q pads.