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2008 International SoC Design Conference最新文献

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Reconfigurable motion estimation architecture design on H.264/AVC for power aware mobile application 基于H.264/AVC的可重构运动估计架构设计
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815618
Yu-Nan Pan, De-Yuan Shen, T. Tsai
{"title":"Reconfigurable motion estimation architecture design on H.264/AVC for power aware mobile application","authors":"Yu-Nan Pan, De-Yuan Shen, T. Tsai","doi":"10.1109/SOCDC.2008.4815618","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815618","url":null,"abstract":"The multimedia system on the mobile is becoming universal, and the multimedia technology has made a significant progress. A mobile device generally with a limited power but is very powerful to support multimedia functions, such as the real-time video communication, movie watching, video and photo capture. In order to support this high computation complexity with the limited power, a power aware architecture is necessary. In a video system, motion estimation has the highest computation complexity. Therefore, in this paper, a concept of a power aware motion estimation architecture design is introduced. The architecture integrated the FS and the Edge Information Mode Decision (EIMD) + Predict Hexagon Search (PHS). With some reconfigurable issues, this architecture achieved the real-time specification with different power status.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128016397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of low-power and high-speed receiver for mobile display module 低功耗高速移动显示模块接收机的设计
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815741
Cheon-Hyo Lee, Jeong-Hoon Kim, Jae-Hyung Lee, Liyan Jin, Yong-Hu Yin, Ji-Hye Jang, Min-cheol Kang, P. Ha, Young-Hee Kim
{"title":"Design of low-power and high-speed receiver for mobile display module","authors":"Cheon-Hyo Lee, Jeong-Hoon Kim, Jae-Hyung Lee, Liyan Jin, Yong-Hu Yin, Ji-Hye Jang, Min-cheol Kang, P. Ha, Young-Hee Kim","doi":"10.1109/SOCDC.2008.4815741","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815741","url":null,"abstract":"We newly proposed a low-power and high-speed mobile display digital interface (MDDI) client receiver in this paper. The receiver was designed as a low-power circuit which had a constant current dissipation over variations of the common-mode voltage (VCM) and power supply voltage, and was able to operate at a rate of 450 Mbps or above under the conditions of a power supply of 3.3 V and a temperature range of -40 to 85degC. A test chip was manufactured with the 0.35 mum CMOS process. When a test was done with a function generator, the data receiver and data recovery circuit were functioning normally.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130581769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
System-On-Chip technology-based on-the-fly audio data acquisition, monitoring and displaying system using FPGA 基于片上系统技术的实时音频数据采集、监控和显示系统采用FPGA
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815611
Mohammed Abdallah, O. Elkeelany
{"title":"System-On-Chip technology-based on-the-fly audio data acquisition, monitoring and displaying system using FPGA","authors":"Mohammed Abdallah, O. Elkeelany","doi":"10.1109/SOCDC.2008.4815611","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815611","url":null,"abstract":"Data monitoring can be defined as signals and waveforms capturing and processing to obtain desired information. Prior to data monitoring, a data acquisition component may be applied. The data acquisition component utilizes sensors that convert any measurement parameter to an electrical signal, which can be monitored and displayed into a display module. Displaying data on the field on-the-fly is needed in many applications. In this research, a novel reconfigurable system design and implementation are proposed using system-on-chip technology. This proposed system is responsible for real-time varying audio data acquisition, analog to digital conversion, processing the digital data, and displaying the data into a display module.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131110637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
High performance NoC architecture for two hidden layers BP Neural Network 两隐层BP神经网络的高性能NoC架构
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815624
Dong Yiping, W. Takahiro
{"title":"High performance NoC architecture for two hidden layers BP Neural Network","authors":"Dong Yiping, W. Takahiro","doi":"10.1109/SOCDC.2008.4815624","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815624","url":null,"abstract":"Artificial neural networks (ANNs) are widely used in applications of an intelligent system such as pattern recognition, fuzzy system, optimization and control. We have already proposed a novel NoC architecture for different kinds of BPANNs and it was shown that the architecture is a promising hardware implementation for Neural Network. However, some problems to be solved are still remained. One of them is performance. In this paper, we propose another NoC architecture, network topology and routing strategy for higher performance. Experimental results by NoC simulator show that this new architecture and routing strategy reduce the communication load, reduce both latency by 7.7% and dynamic power consumption by 10.3% and also improve throughput by 8.1%, all compared with the previous one.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128830062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The Javelin: A Java accelerator based on hardware translation method Javelin:一个基于硬件翻译方法的Java加速器
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815648
Jong-Sung Lee, Hyun-Gyu Kim
{"title":"The Javelin: A Java accelerator based on hardware translation method","authors":"Jong-Sung Lee, Hyun-Gyu Kim","doi":"10.1109/SOCDC.2008.4815648","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815648","url":null,"abstract":"In this paper, we propose a Java accelerator named Javelin (Java enhanced language interpreter) based on a hardware translation method. To overcome performance hurdles in translation based accelerators, we assign registers in the host processor for frequently accessed pointers, entries of the stack, local variables, and intermediate values during bytecode execution. We propose an operand exchange unit (OPEXU) for maximizing compatibility and a stack management unit (SMU) with a smart exception handler for minimizing the overhead by stack exceptions. Javelin increases hardware cost less than 9,000 gates including a 256-byte SRAM and does not decrease the clock frequency of host processor. In our experiments, Javelin provides approximately 24.3 times better performance than that of the pure software VM in terms of execution time and it also reduces the memory traffic during Java processing about 81.9%. Consequently, Javelin provides an energy efficient solution for Java processing.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121111968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low power ZigBee baseband processor 一种低功耗ZigBee基带处理器
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815569
Kai Chen, Hsi-Pin Ma
{"title":"A low power ZigBee baseband processor","authors":"Kai Chen, Hsi-Pin Ma","doi":"10.1109/SOCDC.2008.4815569","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815569","url":null,"abstract":"This paper presents an IEEE 802.15.4 (ZigBee) practicable baseband processor including transmitter and receiver. To estimate and compensate carrier phase error at baseband, the receiver allows full digital solution for carrier phase synchronization. An existing packet detection algorithm for spread spectrum communication system is used to estimate large carrier frequency offset. This paper also presents a new decision-feedback algorithm for residue phase error tracking. The proposed receiver achieves system performance as PER = 0.01 at SNR less than 5 dB, which is better than standard specifications. The baseband processor was implemented in simple hardware architecture and designed with low power technique. The chip is fabricated with the TSMC 0.18 mum 1P6M CMOS technology with a gate count of 78 k. The area is 1.633 mm times 1.633 mm, and power consumption is about 1.7 mW at receiver mode under supply voltage of 1.8 V and operating frequency of 4 MHz.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121241233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A L1-Band RF receiver for GPS aplication in 0.13um CMOS technology 基于0.13um CMOS技术的GPS l1波段射频接收机
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815666
Hoohyun Cho, Younggun Pu, Sangwook Kim, Young-Sik Kim, Kangyoon Lee, Sunjun Ko, Heonchul Park
{"title":"A L1-Band RF receiver for GPS aplication in 0.13um CMOS technology","authors":"Hoohyun Cho, Younggun Pu, Sangwook Kim, Young-Sik Kim, Kangyoon Lee, Sunjun Ko, Heonchul Park","doi":"10.1109/SOCDC.2008.4815666","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815666","url":null,"abstract":"This paper presents a L1-Band RF receiver for GPS application in 0.13 mum CMOS technology. The receiver is based on a 4.092 MHz low-IF architecture to alleviate the DC-offset problem. It includes a low-noise amplifier (LNA), a down-conversion mixer, a bandpass filter, and variable gain amplifier (VGA). The gain of VGA is controlled digitally by the digital gain controller and the total dynamic range of the baseband part is 60 dB. The franctional-N frequency synthesizer with sigma-delta modulator is used to allow multiple reference clock frequencies. The phase noise is -123 dB/Hz at 1 MHz offset. The whole receiver dissipates 45 mW with 1.2 V supply. And the system noise figure (NF) is 4 dB.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126868964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parametric yield-aware sign-off flow in 65/45nm 参数产率感知签名流在65/45nm
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815576
Byung-Su Kim, Byoung-Hyun Lee, Hungbok Choi, S. Heo, Jae-Rim Lee, Yong-Cheul Kim, C. Rim, Kyu-Myung Choi
{"title":"Parametric yield-aware sign-off flow in 65/45nm","authors":"Byung-Su Kim, Byoung-Hyun Lee, Hungbok Choi, S. Heo, Jae-Rim Lee, Yong-Cheul Kim, C. Rim, Kyu-Myung Choi","doi":"10.1109/SOCDC.2008.4815576","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815576","url":null,"abstract":"Due to the increased random variations in nanometer silicon process technology as well as voltage and temperature variations, it is very hard to guarantee performance characteristics with traditional corner-based timing analysis method. The variations, together with the issues like crosstalk and jitter, make it difficult to get a good silicon correlation with simulation and to meet target performance. The advent of SSTA(Statistical Static Timing Analysis) gave the opportunity to solve this problem. This paper proposes a parametric yield-aware sign-off environment based on the SSTA technology. With the proposed environment, it is possible to accurately predict the yield data with sigma level at a given target performance. This environment includes a unique methodology to get silicon correlation from various measurement data and to implement a chip with a given sigma level.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130382872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A design guide for 3-stage CMOS nested Gm-C operational amplifier with area or current minimization 一个设计指南的3级CMOS嵌套Gm-C运算放大器与面积或电流最小化
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815671
Jae-Seung Lee, J. Sim, Hong-June Park
{"title":"A design guide for 3-stage CMOS nested Gm-C operational amplifier with area or current minimization","authors":"Jae-Seung Lee, J. Sim, Hong-June Park","doi":"10.1109/SOCDC.2008.4815671","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815671","url":null,"abstract":"A systematic design guide for 3-stage CMOS operational amplifier (op amp) with nested Gm-C frequency compensation (NGCC) was proposed. With the given specification such as gain-bandwidth (GB), the ratio of high frequency pole to GB, phase margin, input common-mode range, and load capacitance, the guide generates the design parameters that minimize total area or current. The test chip designed by the proposed guide was fabricated with a 0.18-mum CMOS process. The simulation results show reasonable performances with 1.2-V supply voltage, and the measurement results show low-voltage operations of the designed op amps with 0.6-V supply voltage.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130481394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Energy-saving techniques for low-power graphics processing unit 低功耗图形处理单元的节能技术
2008 International SoC Design Conference Pub Date : 2008-11-01 DOI: 10.1109/SOCDC.2008.4815617
Chia-Ming Chang, Shao-Yi Chien, You-Ming Tsao, Chih-Hao Sun, K. Lok, Yu-Jung Cheng
{"title":"Energy-saving techniques for low-power graphics processing unit","authors":"Chia-Ming Chang, Shao-Yi Chien, You-Ming Tsao, Chih-Hao Sun, K. Lok, Yu-Jung Cheng","doi":"10.1109/SOCDC.2008.4815617","DOIUrl":"https://doi.org/10.1109/SOCDC.2008.4815617","url":null,"abstract":"This paper presents a graphics processing unit with energy-saving techniques. Several techniques and architectures are proposed to achieve high performance with low power consumption. First of all, low power core pipeline is designed with 2-issue VLIW architecture to reduce power consumption while achieving the processing capability of 400MFLOPS or 800MOPS. In addition, inter/intra adaptive mutli-threading scheme can increase the performance by increasing hardware utilization, and the proposed configurable memory array architecture can reduce off-chip memory accessing frequency by caching both input data and output results. Furthermore, for graphics applications, a geometry-content-aware technique called early-rejection-after-transformation is proposed to remove redundant operations for invisible triangles. As for circuit level power reduction, power-aware frequency scaling is proposed to further reduce the power consumption.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"296 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131638455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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