A design guide for 3-stage CMOS nested Gm-C operational amplifier with area or current minimization

Abstract

A systematic design guide for 3-stage CMOS operational amplifier (op amp) with nested Gm-C frequency compensation (NGCC) was proposed. With the given specification such as gain-bandwidth (GB), the ratio of high frequency pole to GB, phase margin, input common-mode range, and load capacitance, the guide generates the design parameters that minimize total area or current. The test chip designed by the proposed guide was fabricated with a 0.18-mum CMOS process. The simulation results show reasonable performances with 1.2-V supply voltage, and the measurement results show low-voltage operations of the designed op amps with 0.6-V supply voltage.