PDSDL: A dynamic System Description Language

Abstract

In this paper, we present a new System Description Language (SDL): PDSDL (Python based dynamic system description language). It is used in system modeling and verification, even it can be synthesized to a hardware description language (e.g. Verilog) for implementation on FPGA or ASIC. PDSDL promises to be more flexible and productive than prevalent SystemC. (1) Different from SystemC, it uses Python language other than C/C++ to enjoy the massive merits. (2)Though they both add necessary system related properties to a general-purpose language to achieve their goals, they differ greatly in essence. PDSDL innovatively proposes the dynamic system concept. The modeling, verification and synthesis all rely on the properties of the dynamic changeable system, not the static description in related storage. In addition, Dynamic system enables more efficient design-space exploration by using artificial intelligent method. As a use case, we apply PDSDL to our real-time embedded Java processor design. From our experience, it can speed up productivity at least 5. In addition, the difficulty to develop further tool chain is reduced.