{"title":"一个基于顶点着色器的tessellator，用于带宽高效的移动3D图形","authors":"Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, L. Kim","doi":"10.1109/SOCDC.2008.4815753","DOIUrl":null,"url":null,"abstract":"A tessellation-enabled shader (TES), 1/250 memory bandwidth saving geometry processor, is proposed for a mobile 3D graphics engine. On-chip vertex generation of tessellation is implemented with 6.2% additional logic gate to a conventional vertex shader. An optimized vector dot product unit, a slim special function unit, and a unified data fetch unit reduce 25.6% of area. Dual-core of TES is fabricated using 0.18 um CMOS technology and processes 120 Mvertices/s at 100 MHz while consuming 272 mW of power.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A tessellator based on a vertex shader for bandwidth-efficient mobile 3D graphics\",\"authors\":\"Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, L. Kim\",\"doi\":\"10.1109/SOCDC.2008.4815753\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A tessellation-enabled shader (TES), 1/250 memory bandwidth saving geometry processor, is proposed for a mobile 3D graphics engine. On-chip vertex generation of tessellation is implemented with 6.2% additional logic gate to a conventional vertex shader. An optimized vector dot product unit, a slim special function unit, and a unified data fetch unit reduce 25.6% of area. Dual-core of TES is fabricated using 0.18 um CMOS technology and processes 120 Mvertices/s at 100 MHz while consuming 272 mW of power.\",\"PeriodicalId\":405078,\"journal\":{\"name\":\"2008 International SoC Design Conference\",\"volume\":\"73 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International SoC Design Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCDC.2008.4815753\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International SoC Design Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCDC.2008.4815753","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
提出了一种用于移动3D图形引擎的支持镶嵌的着色器(TES)，节省1/250内存带宽的几何处理器。片上顶点生成是通过在传统顶点着色器上增加6.2%的逻辑门来实现的。优化的矢量点积单元、瘦身的特殊功能单元和统一的数据提取单元，面积减少了25.6%。TES的双核采用0.18 um CMOS技术制造，在100 MHz下处理120 Mvertices/s，消耗272 mW功率。
A tessellator based on a vertex shader for bandwidth-efficient mobile 3D graphics
A tessellation-enabled shader (TES), 1/250 memory bandwidth saving geometry processor, is proposed for a mobile 3D graphics engine. On-chip vertex generation of tessellation is implemented with 6.2% additional logic gate to a conventional vertex shader. An optimized vector dot product unit, a slim special function unit, and a unified data fetch unit reduce 25.6% of area. Dual-core of TES is fabricated using 0.18 um CMOS technology and processes 120 Mvertices/s at 100 MHz while consuming 272 mW of power.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
