{"title":"Analysis on light attenuation through multi-metal-layers for CMOS image sensors on system LSIs","authors":"Yun-Kyung Kim, M. Ikeda, K. Asada","doi":"10.1109/SOCDC.2008.4815581","DOIUrl":null,"url":null,"abstract":"This paper proposes a method for analysis of spectral characteristics on multilayer interconnection. With CMOS technology's downscaling, interconnect layers are multi-stratified since the number of metal levels has increased. However, this multilayer interconnection affects sensitivity of CMOS image sensors. To evaluate the effect on the multilayer interconnect of standard CMOS process technologies, we have developed a method for calculating transferred light intensity through the multilayer interconnect. We show the calculation results in case of standard CMOS 65 nm, 90 nm, 0.18 mum, 0.35 mum, 0.6 mum, and 1.2 mum process technologies.","PeriodicalId":405078,"journal":{"name":"2008 International SoC Design Conference","volume":"01 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International SoC Design Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCDC.2008.4815581","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper proposes a method for analysis of spectral characteristics on multilayer interconnection. With CMOS technology's downscaling, interconnect layers are multi-stratified since the number of metal levels has increased. However, this multilayer interconnection affects sensitivity of CMOS image sensors. To evaluate the effect on the multilayer interconnect of standard CMOS process technologies, we have developed a method for calculating transferred light intensity through the multilayer interconnect. We show the calculation results in case of standard CMOS 65 nm, 90 nm, 0.18 mum, 0.35 mum, 0.6 mum, and 1.2 mum process technologies.