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Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)最新文献

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BP-based learning system with analog neuro-LSI 基于bp的模拟神经- lsi学习系统
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986286
Y. Todo, T. Takasaki, M. Yoshida, T. Yoneyama, H. Asai
{"title":"BP-based learning system with analog neuro-LSI","authors":"Y. Todo, T. Takasaki, M. Yoshida, T. Yoneyama, H. Asai","doi":"10.1109/MWSCAS.2001.986286","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986286","url":null,"abstract":"This paper describes the fabrication of analog neuro-LSI and a learning system with the neuro-LSI, which uses the output of neuro-LSI for learning. First, the design and fabrication of the multi-layer neural network are shown. Next, the construction of learning system with Labview is described and the system performance is estimated. Finally, we show that this system can cancel the fluctuation of analog LSIs and is useful and practical.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126500526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Voltage regulator module with interleaved synchronous buck converters and novel voltage-mode hysteretic control 具有交错同步降压变换器和新型电压型迟滞控制的稳压模块
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986350
J. A. Abu Qahouq, Jia Luo, I. Batarseh
{"title":"Voltage regulator module with interleaved synchronous buck converters and novel voltage-mode hysteretic control","authors":"J. A. Abu Qahouq, Jia Luo, I. Batarseh","doi":"10.1109/MWSCAS.2001.986350","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986350","url":null,"abstract":"Today's on-board low-voltage, high-current DC-DC voltage regulator module (VRM) requirements for the new generation of ICs and microprocessors are increasingly becoming stricter than ever, as the demand for high dynamic performance and high power density converters continues to increase. A new scheme that combines an interleaved technique and voltage-mode hysteretic control approach, by upgrading an existing single-phase chip, is proposed. It is expected that the new combined approach, with some design tradeoffs, will meet many of today's VRM requirements.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130921468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Prototyping design of a transceiver for the new double bitrate DECT 新型双比特率DECT的收发器原型设计
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986189
J.A. Lopez, C. Carreras, O. Nieto-Taladriz
{"title":"Prototyping design of a transceiver for the new double bitrate DECT","authors":"J.A. Lopez, C. Carreras, O. Nieto-Taladriz","doi":"10.1109/MWSCAS.2001.986189","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986189","url":null,"abstract":"This paper presents the prototyping process for the implementation of the digital blocks of a wireless DECT transceiver that doubles the bit rate of the standard, placing special emphasis on the methodologies developed for architecture generation and wordlength validation. Some implementation results are also given at the end of the paper.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127663424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimal mapping from chromosome space to feature space for solving sequential pattern recognition problems 从染色体空间到特征空间的最优映射解决序列模式识别问题
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986242
M. Zohdy, D. Bouchaffra, J. Quinlan
{"title":"Optimal mapping from chromosome space to feature space for solving sequential pattern recognition problems","authors":"M. Zohdy, D. Bouchaffra, J. Quinlan","doi":"10.1109/MWSCAS.2001.986242","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986242","url":null,"abstract":"In this paper we present a method for modeling a genetic algorithm for a sequential pattern recognition problem. This genetic algorithm is shown to be useful in obtaining particular solutions; similarities between particular solutions give a general solution. Transition between chromosome space and feature space is done through relating genes to inputs, based on the discrete nature of both spaces.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"6 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116475411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Optimized parallel implementation of polynomial approximation math functions on a DSP processor 多项式近似数学函数在DSP处理器上的优化并行实现
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986183
Mei Yang, Jinchu Wang, Yuke Wang, S. Zheng
{"title":"Optimized parallel implementation of polynomial approximation math functions on a DSP processor","authors":"Mei Yang, Jinchu Wang, Yuke Wang, S. Zheng","doi":"10.1109/MWSCAS.2001.986183","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986183","url":null,"abstract":"This paper presents a general method to implement polynomial approximation math functions on TMS320C67X architecture with multiple parallel execution units. Our method consists of grain packing, mapping and scheduling to reduce data dependency overhead and fully utilize delay slots. Experimental results of our method on TMS320C67x have achieved up to 70.2% performance improvement over 'C67x library functions.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125660373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Networking highly mobile users using several multi-band phased array antennas 网络高度移动用户使用多个多波段相控阵天线
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986199
J. Foshee, R.S. Tahim, K. Chang
{"title":"Networking highly mobile users using several multi-band phased array antennas","authors":"J. Foshee, R.S. Tahim, K. Chang","doi":"10.1109/MWSCAS.2001.986199","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986199","url":null,"abstract":"The need to network several mobile terminals to exchange high value information brings together a range of technologies. This paper describes a multi-band, multi-functional phased array antenna design that is well suited for networking of several phased antennas on an airborne platform to accomplish wide coverage and for reliable transfer of high value data among the users. The phased array antenna design operates from 8-40 GHz, without switching or reconfiguration. A number of phased array antenna networking options are described each of which provides an efficient approach in accomplishing a system implementation.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125264822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Positive feedback CMOS charge-pump circuits for PLL applications 锁相环应用的正反馈CMOS电荷泵电路
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986317
E. J. Hernández, A. Diaz Sanchez
{"title":"Positive feedback CMOS charge-pump circuits for PLL applications","authors":"E. J. Hernández, A. Diaz Sanchez","doi":"10.1109/MWSCAS.2001.986317","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986317","url":null,"abstract":"Two new charge-pump topologies for RF applications are presented. Their switching speed is increased by using positive feedback, while the power consumption is reduced with current reuse paths. Simulation results for a 0.35 /spl mu/m AMS CMOS technology parameters, shows the feasibility of both structures for low-voltage high-frequency applications.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"445 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132414020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Multilevel monolithic 3D inductors on silicon 硅基多电平单片三维电感
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986321
Ju-Ho Son, Sun-Hong Kim, S. Choi, DoHwan Rho, Dong-Yong Kim
{"title":"Multilevel monolithic 3D inductors on silicon","authors":"Ju-Ho Son, Sun-Hong Kim, S. Choi, DoHwan Rho, Dong-Yong Kim","doi":"10.1109/MWSCAS.2001.986321","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986321","url":null,"abstract":"This paper has been the analysis of passive devices in Si RF and microwave. Multilevel monolithic 3D inductors implemented in a standard CMOS technology are presented. Since on-chip inductors are constrained to be planar, the typical solution is to form a spiral. Proposed inductors are composed of 3D structures requiring no extra processing steps. Inductances are higher in increasing the mutual inductance besides the self-inductance. In this reason, this structure gives rise to a quality factor Q and a inductance using 3D geometry in small areas.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132302139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Logic BIST architecture for FPGAs fpga的逻辑BIST架构
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986207
M. Niamat, P. Mohan
{"title":"Logic BIST architecture for FPGAs","authors":"M. Niamat, P. Mohan","doi":"10.1109/MWSCAS.2001.986207","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986207","url":null,"abstract":"In this paper, we propose a built-in-self-test (BIST) based approach for testing the configurable logic blocks of FPGAs. BIST technique, when applied to a FPGA, does not need any additional testing circuitry. BIST logic is programmed into the FPGA in test mode and the FPGA is reprogrammed to perform its normal function once testing is completed. This effectively eliminates the need for any additional design-for-test circuitry.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116685282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Effects of active microwave device parameters on microwave harmonic frequency generators 有源微波器件参数对微波谐波频率发生器的影响
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986302
J. Johnson, G. Branner, M. Chee
{"title":"Effects of active microwave device parameters on microwave harmonic frequency generators","authors":"J. Johnson, G. Branner, M. Chee","doi":"10.1109/MWSCAS.2001.986302","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986302","url":null,"abstract":"Modern microwave and RF systems are increasingly utilizing internal frequency upconversion techniques. This paper develops improved methods of designing active microwave frequency multipliers utilizing MESFET and HEMT devices. The methods extend and improve the accuracy of classical techniques developed over the past few years.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117191847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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