{"title":"CMOS current mode flash analog to digital converter","authors":"J. A. Bell, J. Bruce, B. Blalock, P. Stubberud","doi":"10.1109/MWSCAS.2001.986166","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986166","url":null,"abstract":"A high speed CMOS current mode flash analog to digital converter is proposed. The design uses a generic cell structure that decreases circuit area for large implementations of the design. A single cell is tested for design constraints, and design constraint solutions are discussed.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"58 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132562275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Nonlinear charge modeling for FET large-signal simulation and its importance for IP3 and ACPR in communication circuits","authors":"D. Root","doi":"10.1109/MWSCAS.2001.986300","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986300","url":null,"abstract":"Nonlinear charge-storage (capacitance) characteristics are significant contributors to FET large-signal performance, determining, along with the well-known current-source nonlinearities, the figures of merit important for communication circuits such as PAE, IP3, and ACPR. This paper reviews the general theory and practice of nonlinear two port charge-storage modeling for FET devices. Topics covered include identification of nonlinear capacitances from measured data, transcapacitances, the modeling constraints of terminal charge conservation and energy conservation and their consequences, and the necessary and sufficient conditions for the construction of unique device-specific nonlinear charge-based models from experimental device data. This approach is largely independent of process and technology, and is therefore generally applicable to FET devices from Si JFETs and MOSFETs to GaAs and InP HEMTs. The fundamental theory and general methodology are independent of the explicit functional form for the capacitance constitutive (C-V) relations, so they apply equally well to closed form analytical empirical models and table-based models based on interpolation or approximation of measured device characteristics.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128235679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A CMOS current amplifier having prescribed input and output impedance","authors":"I. Filanovsky","doi":"10.1109/MWSCAS.2001.986173","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986173","url":null,"abstract":"The paper describes a new CMOS current amplifier with prescribed input and output impedance. The circuit uses an inverse connection of a modified current conveyor. The calculation of input impedance, current gain and output impedance is given. The most demanding design parameter is the input impedance: it has an inductive component forcing this impedance to increase with frequency long before the current gain or output impedance deteriorates. The results of calculations are verified with simulations.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116788033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Gas load forecasting model input factor identification using a genetic algorithm","authors":"Hui Li. Lim, R. Brown","doi":"10.1109/MWSCAS.2001.986277","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986277","url":null,"abstract":"Genetic algorithms (GAs) are used as a tool to identify the input factors for an hourly gas load forecasting model. The proposed model can provide up to 106 hours of load forecasts. Experiences obtained during the application of GA for determination of inputs are discussed. Linear regression based models using the results of this study had an average error 23% less than the existing method at one gas utility over six service areas.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123452908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Kaluri, W. Leong, Kah-Howe Tan, L. Johnson, M. Soderstrand
{"title":"Comparison of RNS and optimized FIR digital filters in Xilinx FPGA's","authors":"K. Kaluri, W. Leong, Kah-Howe Tan, L. Johnson, M. Soderstrand","doi":"10.1109/MWSCAS.2001.986206","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986206","url":null,"abstract":"Highly efficient implementations of FIR digital filters in Xilinx Virtex FPGA's are possible by using scaling, order augmentation and optimized CSD techniques for fixed coefficient multipliers. Addition of Residue Number System (RNS) arithmetic techniques to this approach results in further reduction in FPGA resources particularly when large input and output word lengths are required. RNS is particularly attractive when key operations can be carried out with Look-Up-Table (LUT) techniques using either the block or distributed RAM's in FPGA's or the small LUT's available in each CLB of the Xilinx Virtex FPGA's.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123454623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Repperger, J. Berlin, S. Heinrichs, K. Heinrichs
{"title":"A wireless MEMS application with dynamic data and strap support system","authors":"D. Repperger, J. Berlin, S. Heinrichs, K. Heinrichs","doi":"10.1109/MWSCAS.2001.986288","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986288","url":null,"abstract":"A wireless MEMS force/pressure/temperature sensor was utilized in the collection of data from a study involving a strap support system to be used in conjunction with human subjects. Both static and dynamic data were collected to demonstrate the efficacy of the sensor described herein. The wireless property and ability to place the sensor at arbitrary points provides great utility for the application of such a MEMS apparatus.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126173490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and implementation of an MRC-C TQE filter with on-chip automatic tuning","authors":"H. Martínez, E. Vidal, E. Alarcón, A. Poveda","doi":"10.1109/MWSCAS.2001.986148","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986148","url":null,"abstract":"This work describes the design and implementation of the tuning loops (both central frequency and quality factor control loops) for a bandpass continuous-time fully-balanced filter based on a modification of the Transimpedance Q-Enhancement (TQE) structure, intended for audio-band applications. The circuit has been designed and fabricated in a CMOS 0.8 /spl mu/m technology, and MRC (MOS Resistive Circuit) cells have been used to implement electronically tunable active resistors. Both post-layout transistor-level simulation results and experimental results validate the functionality of the tuning system.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123920410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"RISC system design in an FPGA","authors":"J. Luker, V. Prasad","doi":"10.1109/MWSCAS.2001.986247","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986247","url":null,"abstract":"Known for their flexibility, Field Programmable Gate Arrays (FPGA) are widely used for ASIC emulation, glue-logic consolidation, or as a solution for applications with high volatility. FPGAs facilitate quick time to market, and their incredible power of re-programmability often makes them the heart of a system. This paper presents the design of a Reduced Instruction Set Computer (RISC) system described using VHDL and the results of researching the implementation of this system in an FPGA. This RISC is a 16-bit processor with high general-purpose register (GPR) orthogonality and communicates to peripheral devices via a serial bus.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123930807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An investigation into adiabatic circuits","authors":"S. Sompur, Yong-Bin Kim","doi":"10.1109/MWSCAS.2001.986171","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986171","url":null,"abstract":"In this paper we discuss some of the results obtained when we conducted an investigation into adiabatic circuits. We provide theoretical proof of power savings in adiabatic circuits when, compared to standard static CMOS circuits and relate the power savings as a function of the charging/discharging time. We provide experimental results to support our claim. In addition to this, we also provide results of our study into basic gates such as Nand, Nor, Xnor and more complicated circuits like a 4 and 8-bit adder.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124045752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A blind spatial-temporal adaptive equalizer with array antenna using second order statistics","authors":"H. Hayashi, H. Ochi","doi":"10.1109/MWSCAS.2001.986196","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986196","url":null,"abstract":"It is known that signal processing with TDL (tapped-delay-line) spatial-temporal array antennas improve communication quality since they can suppress simultaneously undesired signals with space domain processing and ISI with time domain processing. However, conventional array antennas require training sequences to update tap coefficients. Such methods have to waste a fraction of the transmission time to transmit training sequences. In this paper., we propose a novel spatial-temporal blind array antenna using second order statistics, which does not need training sequences. The proposed algorithm can be applied to the environment in which one transmitter with narrow band signal and white noise or broadband signal exist over the channel. Some computer simulations are shown to verify the effectiveness of the proposed method.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130395717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}