Comparison of RNS and optimized FIR digital filters in Xilinx FPGA's

Abstract

Highly efficient implementations of FIR digital filters in Xilinx Virtex FPGA's are possible by using scaling, order augmentation and optimized CSD techniques for fixed coefficient multipliers. Addition of Residue Number System (RNS) arithmetic techniques to this approach results in further reduction in FPGA resources particularly when large input and output word lengths are required. RNS is particularly attractive when key operations can be carried out with Look-Up-Table (LUT) techniques using either the block or distributed RAM's in FPGA's or the small LUT's available in each CLB of the Xilinx Virtex FPGA's.