RISC system design in an FPGA

Known for their flexibility, Field Programmable Gate Arrays (FPGA) are widely used for ASIC emulation, glue-logic consolidation, or as a solution for applications with high volatility. FPGAs facilitate quick time to market, and their incredible power of re-programmability often makes them the heart of a system. This paper presents the design of a Reduced Instruction Set Computer (RISC) system described using VHDL and the results of researching the implementation of this system in an FPGA. This RISC is a 16-bit processor with high general-purpose register (GPR) orthogonality and communicates to peripheral devices via a serial bus.