fpga的逻辑BIST架构

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI:10.1109/MWSCAS.2001.986207

M. Niamat, P. Mohan

{"title":"fpga的逻辑BIST架构","authors":"M. Niamat, P. Mohan","doi":"10.1109/MWSCAS.2001.986207","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a built-in-self-test (BIST) based approach for testing the configurable logic blocks of FPGAs. BIST technique, when applied to a FPGA, does not need any additional testing circuitry. BIST logic is programmed into the FPGA in test mode and the FPGA is reprogrammed to perform its normal function once testing is completed. This effectively eliminates the need for any additional design-for-test circuitry.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Logic BIST architecture for FPGAs\",\"authors\":\"M. Niamat, P. Mohan\",\"doi\":\"10.1109/MWSCAS.2001.986207\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a built-in-self-test (BIST) based approach for testing the configurable logic blocks of FPGAs. BIST technique, when applied to a FPGA, does not need any additional testing circuitry. BIST logic is programmed into the FPGA in test mode and the FPGA is reprogrammed to perform its normal function once testing is completed. This effectively eliminates the need for any additional design-for-test circuitry.\",\"PeriodicalId\":403026,\"journal\":{\"name\":\"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-08-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2001.986207\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2001.986207","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

在本文中，我们提出了一种基于内置自检(BIST)的方法来测试fpga的可配置逻辑块。当应用于FPGA时，BIST技术不需要任何额外的测试电路。在测试模式下将BIST逻辑编程到FPGA中，一旦测试完成，FPGA将被重新编程以执行其正常功能。这有效地消除了任何额外的测试设计电路的需要。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Logic BIST architecture for FPGAs

In this paper, we propose a built-in-self-test (BIST) based approach for testing the configurable logic blocks of FPGAs. BIST technique, when applied to a FPGA, does not need any additional testing circuitry. BIST logic is programmed into the FPGA in test mode and the FPGA is reprogrammed to perform its normal function once testing is completed. This effectively eliminates the need for any additional design-for-test circuitry.

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Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

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