Logic BIST architecture for FPGAs

Abstract

In this paper, we propose a built-in-self-test (BIST) based approach for testing the configurable logic blocks of FPGAs. BIST technique, when applied to a FPGA, does not need any additional testing circuitry. BIST logic is programmed into the FPGA in test mode and the FPGA is reprogrammed to perform its normal function once testing is completed. This effectively eliminates the need for any additional design-for-test circuitry.