Ju-Ho Son, Sun-Hong Kim, S. Choi, DoHwan Rho, Dong-Yong Kim
{"title":"硅基多电平单片三维电感","authors":"Ju-Ho Son, Sun-Hong Kim, S. Choi, DoHwan Rho, Dong-Yong Kim","doi":"10.1109/MWSCAS.2001.986321","DOIUrl":null,"url":null,"abstract":"This paper has been the analysis of passive devices in Si RF and microwave. Multilevel monolithic 3D inductors implemented in a standard CMOS technology are presented. Since on-chip inductors are constrained to be planar, the typical solution is to form a spiral. Proposed inductors are composed of 3D structures requiring no extra processing steps. Inductances are higher in increasing the mutual inductance besides the self-inductance. In this reason, this structure gives rise to a quality factor Q and a inductance using 3D geometry in small areas.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Multilevel monolithic 3D inductors on silicon\",\"authors\":\"Ju-Ho Son, Sun-Hong Kim, S. Choi, DoHwan Rho, Dong-Yong Kim\",\"doi\":\"10.1109/MWSCAS.2001.986321\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper has been the analysis of passive devices in Si RF and microwave. Multilevel monolithic 3D inductors implemented in a standard CMOS technology are presented. Since on-chip inductors are constrained to be planar, the typical solution is to form a spiral. Proposed inductors are composed of 3D structures requiring no extra processing steps. Inductances are higher in increasing the mutual inductance besides the self-inductance. In this reason, this structure gives rise to a quality factor Q and a inductance using 3D geometry in small areas.\",\"PeriodicalId\":403026,\"journal\":{\"name\":\"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)\",\"volume\":\"93 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-08-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2001.986321\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2001.986321","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper has been the analysis of passive devices in Si RF and microwave. Multilevel monolithic 3D inductors implemented in a standard CMOS technology are presented. Since on-chip inductors are constrained to be planar, the typical solution is to form a spiral. Proposed inductors are composed of 3D structures requiring no extra processing steps. Inductances are higher in increasing the mutual inductance besides the self-inductance. In this reason, this structure gives rise to a quality factor Q and a inductance using 3D geometry in small areas.