{"title":"Voltage regulator module with interleaved synchronous buck converters and novel voltage-mode hysteretic control","authors":"J. A. Abu Qahouq, Jia Luo, I. Batarseh","doi":"10.1109/MWSCAS.2001.986350","DOIUrl":null,"url":null,"abstract":"Today's on-board low-voltage, high-current DC-DC voltage regulator module (VRM) requirements for the new generation of ICs and microprocessors are increasingly becoming stricter than ever, as the demand for high dynamic performance and high power density converters continues to increase. A new scheme that combines an interleaved technique and voltage-mode hysteretic control approach, by upgrading an existing single-phase chip, is proposed. It is expected that the new combined approach, with some design tradeoffs, will meet many of today's VRM requirements.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2001.986350","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17
Abstract
Today's on-board low-voltage, high-current DC-DC voltage regulator module (VRM) requirements for the new generation of ICs and microprocessors are increasingly becoming stricter than ever, as the demand for high dynamic performance and high power density converters continues to increase. A new scheme that combines an interleaved technique and voltage-mode hysteretic control approach, by upgrading an existing single-phase chip, is proposed. It is expected that the new combined approach, with some design tradeoffs, will meet many of today's VRM requirements.