2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)最新文献_第4页

Efficient Discharge Waveform Distribution Measurement Using Active Machine Learning 基于主动机器学习的高效放电波形分布测量

2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2022-12-12 DOI: 10.1109/EDAPS56906.2022.9995150

Yuting Xie, Ling Zhang, Junhui Chen, Da Li, Zhenzhong Yang, Dan Ren, Erping Li

引用次数: 0

A New Current Crowding Phenomenon for Flip-Chip-on-Leadframe (FCOL) Package and its Impact on Electromigration Reliability 引线框架倒装芯片(FCOL)封装中一种新的电流拥挤现象及其对电迁移可靠性的影响

2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2022-12-12 DOI: 10.1109/EDAPS56906.2022.9995226

Sylvester Ankamah-Kusi, Koduri K. Sreenivasan, R. Murugan

引用次数: 0

Hybrid Copper-Graphene Package Interconnects for Channel Loss Improvement in High-Speed Serial Interfaces 高速串行接口中改善通道损耗的混合铜-石墨烯封装互连

2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2022-12-12 DOI: 10.1109/EDAPS56906.2022.9995067

K. Nagarajan, Ajay Kumar Vaidhyanathan, Parthasarathy Ramaswamy, Suyash Kushwaha, Rohit Sharma

{"title":"Hybrid Copper-Graphene Package Interconnects for Channel Loss Improvement in High-Speed Serial Interfaces","authors":"K. Nagarajan, Ajay Kumar Vaidhyanathan, Parthasarathy Ramaswamy, Suyash Kushwaha, Rohit Sharma","doi":"10.1109/EDAPS56906.2022.9995067","DOIUrl":"https://doi.org/10.1109/EDAPS56906.2022.9995067","url":null,"abstract":"Data rates in high-speed interfaces like upcoming PCIe Gen6, SERDES, Ethernet are continuously increasing, and the design specifications are becoming more stringent to ensure required performance. Any small variation in the specifications will have significant impact on signal integrity and affect the performance. This means that the total insertion loss, ISI, non-ISI jitter in the entire interconnect should be improved.IC package plays a key role in signal integrity of the high-speed signal and there is a need to have low loss channel. Standards like PCIe have a loss requirement of 4 dB combining silicon and package, in case of non-root complex. Recent developments suggest new design trends for multi-chiplets in a single package with increasing package sizes, which can make it extremely difficult to predict insertion loss specifications. Conductivity, dielectric properties, and loss tangent drives the overall loss per unit length and the current low-loss materials have insertion loss of around 1 dB per 10 mm. While many advances have been reported in the literature, scope for improvement exists and conventional approaches of lowering DF of dielectric material or reducing the surface roughness of Copper have helped but are not adequate for the demands of high-speed interconnects. This paper proposes a novel approach by using hybrid Copper-Graphene package interconnects, which helps in reducing signal losses and improves the overall performance of the system.","PeriodicalId":401014,"journal":{"name":"2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131139012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IC Package with the system board Interconnects - simulation showing PDN noise due to simultaneous switching IOs and its effect on Signal Integrity 带有系统板互连的IC封装-模拟显示了由于同时切换IOs而产生的PDN噪声及其对信号完整性的影响

2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2022-12-12 DOI: 10.1109/EDAPS56906.2022.9994903

Rajesh Badala Jagadeesh, Venkatesh Ramashastry, Bharath Ramprasad, Surya Prakash Rao Bengaluru Srihari, Satvik Bhat, Vignesh Sunku Radhakrishna

引用次数: 0

Power Integrity and Enablement Challenges for Integrated Dual-Mode Linear Voltage Regulator in Next Generation Intel® Core Microprocessor 下一代Intel®Core微处理器集成双模线性稳压器的电源完整性和实现挑战

2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2022-12-12 DOI: 10.1109/EDAPS56906.2022.9995454

Deeksha Rawat, Chilla Venugopal Reddy, Vishal Gupta, Gaurav Singh

引用次数: 0

Artificial Intelligence based advanced Signal Integrity prediction 基于人工智能的先进信号完整性预测

2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2022-12-12 DOI: 10.1109/EDAPS56906.2022.9995470

Prerna, Nithya Ramalingam, Zaman Zaid Mulla, Archana Ganeshan, Ranjul Balakrishnan, Anoop Karunan

{"title":"Artificial Intelligence based advanced Signal Integrity prediction","authors":"Prerna, Nithya Ramalingam, Zaman Zaid Mulla, Archana Ganeshan, Ranjul Balakrishnan, Anoop Karunan","doi":"10.1109/EDAPS56906.2022.9995470","DOIUrl":"https://doi.org/10.1109/EDAPS56906.2022.9995470","url":null,"abstract":"As the signaling speeds continue to increase, maintaining Signal Integrity (SI) for the complete customer design space is a huge challenge. These constraints, along with the limitations of traditional methods of design space inclusion and channel behavior prediction pose significant risk to system design. Specific focus is needed on design space utilization techniques used for factoring in platform variability. Interfaces like PCIe Gen5/Gen6/Gen4 etc. exhibit higher order behaviors that can’t be modelled by current prediction algorithm like Response Surface Method (RSM). This leads to inaccurate system behavior understanding and results in unreliable platform design recommendations. To minimize design risk and achieve highly reliable scaling of Platform Design Guide (PDG) solution, this paper discusses the implementation of an Artificial Intelligence (AI) based methodology to cover complete design space and predict higher order system behaviors with high accuracy. Current SI method involves RSM type Design of Experiments (DOE) creation and results prediction using second order RSM as shown in Fig. 2(a). It has limitations since RSM uses only three variable levels therefore doesn’t cover the entire design space. It can only model up to second order system behavior. These issues can be addressed using proposed AI based methodology shown in Fig. 2(b). These AI techniques have been encapsulated into an AI based tool called Fitpro which fully automates space filled DOE creation and SI results prediction. Fitpro significantly reduces manual interventions and positively impacts efficiency.","PeriodicalId":401014,"journal":{"name":"2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129137108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Channel Impedance Optimization For 100 Gbps High-Speed Networking Interfaces 100gbps高速网络接口的通道阻抗优化

2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2022-12-12 DOI: 10.1109/EDAPS56906.2022.9994920

Chu Paul, Lin Eva, James Chen, Liao Chun-Lin, Bandi Sathvika, Mallikarjun Vasa, B. Mutnury

{"title":"Channel Impedance Optimization For 100 Gbps High-Speed Networking Interfaces","authors":"Chu Paul, Lin Eva, James Chen, Liao Chun-Lin, Bandi Sathvika, Mallikarjun Vasa, B. Mutnury","doi":"10.1109/EDAPS56906.2022.9994920","DOIUrl":"https://doi.org/10.1109/EDAPS56906.2022.9994920","url":null,"abstract":"High-speed designs today have multiple high-speed interfaces, and these interfaces have different impedance requirements in the same system. For example: PCIe interface is designed for 85 ohms whereas Gigabit ethernet is designed for 100 ohms. Sometimes due to stack-up cross-sectional restrictions and fixed dielectric constant of the material, it is not easy to meet all characteristic impedance requirements in the design. Design trade-off needs to be performed to analyze which interface is sensitive to impedance variations. With signal speeds going above 100 Gbps, pulse amplitude modulation-4 (PAM4) has become more common and PAM4 signaling is more sensitive to impedance variations due to low signal-to-noise ratio (SNR).In this paper, the impact of channel impedance on 100 Gbps ethernet (802.3ck) interface is analyzed using time-domain and frequency domain analysis. Channel operating margin (COM) analysis is performed for various channel impedances on an 802.3ck-CR topology. It Is found that huge impedance mismatch between the trace breakout and channel impacts channel performance adversely.","PeriodicalId":401014,"journal":{"name":"2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126847210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Methodology to Optimize the Number and Placement of Decoupling Capacitors in a Multilevel Power Delivery Network 多电平供电网络中去耦电容数量和位置的优化方法

2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2022-12-12 DOI: 10.1109/EDAPS56906.2022.9995085

R. Krishna, Thong Nguyen, Atom O. Watanabe, D. Becker, Arvind Kumar, E. Rosenbaum

引用次数: 1

A Dual-Band Compact Antenna Array with Scattering Suppression Capability in Low Band 具有低频段散射抑制能力的双频紧凑型天线阵列

2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2022-12-12 DOI: 10.1109/EDAPS56906.2022.9994853

Shiyu Sun, Hong-li Peng, Hongan Zhou, Qingmian Wan

引用次数: 0

ENRZ vs. NRZ: A Performance Comparison at 112 Gbps ENRZ与NRZ: 112 Gbps下的性能比较

2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2022-12-12 DOI: 10.1109/EDAPS56906.2022.9995425

S. Chen, F. de Paulis

引用次数: 0