{"title":"Statistical Method for Eye Diagram Simulation in a High-Speed Link Nonlinear System","authors":"Bobi Shi, Yi Zhou, Thong Nguyen, J. Schutt-Ainé","doi":"10.1109/EDAPS56906.2022.9994885","DOIUrl":"https://doi.org/10.1109/EDAPS56906.2022.9994885","url":null,"abstract":"In this work, an accurate method for the statistical analysis of eye diagrams of nonlinear systems is proposed. The probability density function of a nonlinear input is known and the static memory-less nonlinearity is characterized by a polynomial function. The probability density function of the nonlinear output can thus be estimated through the nonlinear transformation to calculate the final statistical eye diagram.","PeriodicalId":401014,"journal":{"name":"2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132004483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Akhila Purushothaman, Siddharth Rajagopalan, M. Moorthy
{"title":"Multi-lane SerDes Power Delivery Network Challenges and Decap Optimization","authors":"Akhila Purushothaman, Siddharth Rajagopalan, M. Moorthy","doi":"10.1109/EDAPS56906.2022.9995015","DOIUrl":"https://doi.org/10.1109/EDAPS56906.2022.9995015","url":null,"abstract":"As we move into the complex design of high-speed IOs working at increased datarates of more than 100G, power delivery network (PDN) optimization becomes more challenging. To meet the stringent Power Delivery Network noise specifications, we make sure that the impedance seen by the device meets the target impedance, by optimizing the decap (decoupling capacitor) requirements at PCB, package, and die. Package level decap optimization is one of the major challenges to be addressed to meet the voltage ripple requirements with minimal BOM(Bill of Materials) cost. Here we propose a method to perform the decap optimization of the Serdes with a shared power delivery network, considering the impact of power supply noise coupling in multi-lane shared SerDes. This paper analyses the impact on ripple voltage from different voltage noise sources and explains how the PDN design accuracy can be improved in the frequency domain without having to run the transient simulation every time, which is a time-consuming process and poses challenges to Time-to-Market (TTM) concerns.","PeriodicalId":401014,"journal":{"name":"2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129756898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Compensation Amplifier with Automatic Zeroing and Stable Chopping","authors":"Qiliang Liang, M. Tong","doi":"10.1109/EDAPS56906.2022.9995145","DOIUrl":"https://doi.org/10.1109/EDAPS56906.2022.9995145","url":null,"abstract":"This paper proposes a compensation (or error) amplifier with rail-to-rail input and output ranges. The amplifier combines automatic zero adjustment technology and stable chopper to suppress its offset related ripple. Two rail-to-rail input fully differential operational amplifiers in parallel can realize that when one operational amplifier is in the amplification state, the other operational amplifier is in the feedback state. The two amplifiers are interleaved for common mode feedback adjustment, so that the whole compensation amplifier has different states: common mode feedback, offset sampling and amplification. An eight-frequency clock module is integrated in the compensation (or error) amplifier to supply power to each enable end of the amplifier. Finally, it outputs through the third amplifier, which makes the operational amplifier have the advantages of large bandwidth and high accuracy compared with the traditional operational amplifier.","PeriodicalId":401014,"journal":{"name":"2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129980553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Keeyoung Son, Daehwan Lho, Keunwoo Kim, Seonguk Choi, Haeyeon Kim, Hyunwook Park, Boogyo Sim, Hyunwoo Kim, Taein Shin, Joungho Kim
{"title":"Power Distribution Network Impedance Analysis considering Thermal Distribution","authors":"Keeyoung Son, Daehwan Lho, Keunwoo Kim, Seonguk Choi, Haeyeon Kim, Hyunwook Park, Boogyo Sim, Hyunwoo Kim, Taein Shin, Joungho Kim","doi":"10.1109/EDAPS56906.2022.9995613","DOIUrl":"https://doi.org/10.1109/EDAPS56906.2022.9995613","url":null,"abstract":"In this paper, we analyzed a power distribution network (PDN) impedance considering thermal distribution. Due to the development of integrated circuits (ICs) towards high density and high performance, the supply voltage has been reduced while power density has been increased. Shrunk supply voltage causes a low voltage margin and high temperature caused by the high power density varies the circuit parameters of the PDN. Thus, considering the operating temperature effects for a robust PDN design is essential. However, the previous power integrity analysis is not focused on temperature effects on PDN. Hence, impedance analysis of PDN considering thermal distribution is essential. Therefore, this research analyzed thermal distribution effects on the self-impedance of PDN. By using a W-element model, we analyzed thermal distribution effects on PDN self-impedance by circuit simulation. As a result, the difference in self-impedances is observed between the PDNs with other thermal distributions in spite of current loop path and mean temperature; The capacitance has same value as the capacitance considering mean temperature of thermal distribution; The value of the resistance closes to the resistance considering the temperature at the probing point, not the mean temperature.","PeriodicalId":401014,"journal":{"name":"2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130574395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Acceleration of Vector Fitting by Reusing the Householder Reflectors in Multiple QR Factorization","authors":"Chiu-Chih Chou, J. Schutt-Ainé","doi":"10.1109/EDAPS56906.2022.9995103","DOIUrl":"https://doi.org/10.1109/EDAPS56906.2022.9995103","url":null,"abstract":"The classic method of accelerating vector fitting (VF) for a multiport network is to do several small QR factorizations to extract the R22 matrices before solving the least-square system. In the literature and some open-source VF implementations, each QR factorization is performed separately. Taking a closer look at the theory, however, we can see that the first block of the matrices being factorized are the same, which means the computational cost can be reduced if the factorization of this part is skipped. To achieve this goal, however, we cannot simply call the high-level QR functions offered in many computational packages; instead, we must go down to the bottom level of QR factorization and reuse the Householder reflectors directly. In this paper, the theory and implementation of this idea is presented in detail. The theoretic flop reduction is roughly 25%, while in actual tests the time reduction may reach 60%.","PeriodicalId":401014,"journal":{"name":"2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127410917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}