Channel Impedance Optimization For 100 Gbps High-Speed Networking Interfaces

2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2022-12-12 DOI:10.1109/EDAPS56906.2022.9994920

Chu Paul, Lin Eva, James Chen, Liao Chun-Lin, Bandi Sathvika, Mallikarjun Vasa, B. Mutnury

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Abstract

High-speed designs today have multiple high-speed interfaces, and these interfaces have different impedance requirements in the same system. For example: PCIe interface is designed for 85 ohms whereas Gigabit ethernet is designed for 100 ohms. Sometimes due to stack-up cross-sectional restrictions and fixed dielectric constant of the material, it is not easy to meet all characteristic impedance requirements in the design. Design trade-off needs to be performed to analyze which interface is sensitive to impedance variations. With signal speeds going above 100 Gbps, pulse amplitude modulation-4 (PAM4) has become more common and PAM4 signaling is more sensitive to impedance variations due to low signal-to-noise ratio (SNR).In this paper, the impact of channel impedance on 100 Gbps ethernet (802.3ck) interface is analyzed using time-domain and frequency domain analysis. Channel operating margin (COM) analysis is performed for various channel impedances on an 802.3ck-CR topology. It Is found that huge impedance mismatch between the trace breakout and channel impacts channel performance adversely.

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100gbps高速网络接口的通道阻抗优化

当今的高速设计有多个高速接口，而这些接口在同一系统中具有不同的阻抗要求。例如:PCIe接口设计为85欧姆，而千兆以太网设计为100欧姆。有时由于材料的堆积截面限制和介电常数的固定，在设计中不容易满足所有的特性阻抗要求。需要进行设计权衡，以分析哪个接口对阻抗变化敏感。随着信号速度超过100 Gbps，脉冲幅度调制-4 (PAM4)变得越来越普遍，由于低信噪比(SNR)， PAM4信号对阻抗变化更敏感。本文采用时域和频域分析方法，分析了信道阻抗对100gbps以太网(802.3ck)接口的影响。信道运行余量(COM)分析在802.3 k- cr拓扑上执行各种信道阻抗。研究发现，走线与通道之间的巨大阻抗失配会对通道性能产生不利影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)

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