Power Integrity and Enablement Challenges for Integrated Dual-Mode Linear Voltage Regulator in Next Generation Intel® Core Microprocessor

Abstract

A dual mode digital power gate (PG) and linear low drop-out regulator (LDO) is implemented on Intel® next generation™ microprocessor to enable different IPs on the SoC to operate at their minimal voltage levels. This paper discusses post silicon debug and validation techniques to characterize an integrated dual-mode voltage regulator. Performance metrics such as mode transition, power saving, circuit stability and voltage droop are measured and established in this work. These techniques in general can be applied to an integrated linear voltage regulator. The regulated modes are used when load current or ∂i/∂t is low thus allowing better power management in deeper package core states. Measurement shows 11% power saving in the allocated power budget in PKGC10 when voltage regulator is enabled to regulate at 0.7volt output.