{"title":"带有系统板互连的IC封装-模拟显示了由于同时切换IOs而产生的PDN噪声及其对信号完整性的影响","authors":"Rajesh Badala Jagadeesh, Venkatesh Ramashastry, Bharath Ramprasad, Surya Prakash Rao Bengaluru Srihari, Satvik Bhat, Vignesh Sunku Radhakrishna","doi":"10.1109/EDAPS56906.2022.9994903","DOIUrl":null,"url":null,"abstract":"The analysis of package design with the PCB interconnects presented here shows the benefit of signal and power integrity co-simulations with power aware approach to mitigate the signal degradation that are caused by non-ideal behavior of the power distribution network and the simultaneous switching I/Os.","PeriodicalId":401014,"journal":{"name":"2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"IC Package with the system board Interconnects - simulation showing PDN noise due to simultaneous switching IOs and its effect on Signal Integrity\",\"authors\":\"Rajesh Badala Jagadeesh, Venkatesh Ramashastry, Bharath Ramprasad, Surya Prakash Rao Bengaluru Srihari, Satvik Bhat, Vignesh Sunku Radhakrishna\",\"doi\":\"10.1109/EDAPS56906.2022.9994903\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The analysis of package design with the PCB interconnects presented here shows the benefit of signal and power integrity co-simulations with power aware approach to mitigate the signal degradation that are caused by non-ideal behavior of the power distribution network and the simultaneous switching I/Os.\",\"PeriodicalId\":401014,\"journal\":{\"name\":\"2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAPS56906.2022.9994903\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAPS56906.2022.9994903","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
IC Package with the system board Interconnects - simulation showing PDN noise due to simultaneous switching IOs and its effect on Signal Integrity
The analysis of package design with the PCB interconnects presented here shows the benefit of signal and power integrity co-simulations with power aware approach to mitigate the signal degradation that are caused by non-ideal behavior of the power distribution network and the simultaneous switching I/Os.
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