Proceedings. SOS/SOI Technology Workshop最新文献_第6页

Implantation damage in SIMOX structures SIMOX结构的植入损伤

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95419

N. Guillemot, J. Stoemenos, P. Normand, D. Tsoukalas

引用次数: 0

Two-dimensional numerical simulation of short channel SOI transistors 短沟道SOI晶体管的二维数值模拟

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95399

G. A. Armstrong, N. Thomas, J.R. Davis

引用次数: 0

SOI thin film fully depleted high performance devices SOI薄膜全耗尽高性能器件

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95445

T. MacElwee

引用次数: 1

Characteristics of full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material 全蚀刻层转移/绝缘体上硅(FELT/SOI)材料的特性

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95396

S. Malhi, M. Anderson, C.C. Shen, K. Bean, R. Sundaresan, G. Gopffarth, K. Lindberg, D. Yeakley, J. Smith

{"title":"Characteristics of full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material","authors":"S. Malhi, M. Anderson, C.C. Shen, K. Bean, R. Sundaresan, G. Gopffarth, K. Lindberg, D. Yeakley, J. Smith","doi":"10.1109/SOI.1988.95396","DOIUrl":"https://doi.org/10.1109/SOI.1988.95396","url":null,"abstract":"Summary form only given. A full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material process has been developed that meets the following criteria: (1) the material quality is identical to epitaxial silicon layers; (2) the SOI layer thickness is well controlled; (3) the insulator material choice and thickness is variable; (4) the device-to-device isolation is left to customer discretion. In the FELT/SOI process, a p+ etchstop layer is fabricated on a lightly doped starting substrate followed by epitaxial layer deposition with the type and resistivity required for the final SOI layer. Next an insulator layer is either grown or deposited followed by thick polysilicon deposition as is typical in standard DI process. The original substrate is now mechanically ground up to the vicinity of p+ etchstop layer. The remaining silicon overlying the etchstop layer and the etchstop layer itself are then removed in doping sensitive etches followed by surface finish. The SOI layer thickness control over a nominally 10- mu m layer on a 4-in wafer is +or-0.5 mu m, and the layer shows no material defects. Bipolar transistors fabricated on this material and epitaxial control material show comparable performance in terms of high gain sharp junction breakdown, and good yield.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124243424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An analytic model for very thin SOI transistors 超薄SOI晶体管的解析模型

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95415

J.B. McKitterick, A. Caviglia

{"title":"An analytic model for very thin SOI transistors","authors":"J.B. McKitterick, A. Caviglia","doi":"10.1109/SOI.1988.95415","DOIUrl":"https://doi.org/10.1109/SOI.1988.95415","url":null,"abstract":"Summary form only given. Devices made in very thin films (1000 AA or less) have a number of characteristics which are different from those of devices made in bulk material or thick SOI. In order to design these devices properly, it is important to understand these differences. To do this, the authors have derived an approximation to Poisson's equation valid for thin silicon films. This approximation is equivalent to assuming that the silicon film is replaced by a sheet of charge and zero thickness. Although this seems to be a radical approximation, the range of validity is surprisingly wide, primarily because the total dopant charge in these thin films is so small. The results of this simple model indicate that long channel transistors fabricated in thin SOI do have a number of properties that are different from transistors fabricated in thicker SOI films or in bulk films. In particular, the threshold voltages of the transistors are independent of doping (if the transistor is thin enough or lightly doped enough), the threshold voltages are dependent only logarithmically on the thickness of the film (if the total dose remains constant), and the front threshold voltage is linearly dependent on the back gate voltage over a wide range of back gate voltages. The dependence of the subthreshold slope on both the front and back interface-state densities can also be obtained from this model.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121324858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

C-V analysis of ultrathin DSPE SOS 超薄DSPE SOS的C-V分析

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95409

M. Burgener, G. Garcia, R. Reedy

{"title":"C-V analysis of ultrathin DSPE SOS","authors":"M. Burgener, G. Garcia, R. Reedy","doi":"10.1109/SOI.1988.95409","DOIUrl":"https://doi.org/10.1109/SOI.1988.95409","url":null,"abstract":"Summary form only given. Capacitors have been fabricated in thinned double solid phase epitaxial (DSPE) silicon on sapphire (SOS). The silicon films are 100-nm thick and doped with phosphorus to 5e+16/cm/sup 2/. The capacitor structures are gated Hall bars with a polysilicon gate on a 25-nm oxide with the source and drain doped N/sup +/. Capacitance data were taken with a lock-in amplifier at low frequencies. Experimental data indicated four regions in a thin-film C-V plot. Three of these regions are the classic accumulation, inversion, and depletion regions. The fourth region is unique to electrically thin films and is called the fully depleted region. The value of the capacitance in region four has been shown to depend quantitatively on the electrically active traps in thin SOS/SOI structures. Thus a thin-film capacitance voltage plot is a sensitive technique for measuring electrically active traps in SOI structures. A model has been developed that explains C-V plots on the thinned, as-purchased SOS and how that relates to C-V plots on the improved SOS. A computer simulation program was written to solve Poisson's equation exactly and predict C-V plots using the proposed model. On the basis of the simulation, the trap model and data show very good agreement. Reduction of trap levels by a factor of 30 in the DSPE material has been measured.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115656466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Gigahertz CMOS/SIMOX circuits

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95438

J. Colinge, J. Kang, W. McFarland, C. Stout, R. Walker

{"title":"Gigahertz CMOS/SIMOX circuits","authors":"J. Colinge, J. Kang, W. McFarland, C. Stout, R. Walker","doi":"10.1109/SOI.1988.95438","DOIUrl":"https://doi.org/10.1109/SOI.1988.95438","url":null,"abstract":"Summary form only given, as follows. High-speed CMOS logic circuits have been realized in thin-film (100-nm) SIMOX (separation by implantation of oxygen) films annealed at 1250 degrees C. LOCOS (local oxidation of silicon) isolation was used, and the gate oxide thickness was 22 nm. Boron concentration was 1E17 and 5E16 cm/sup -3/ in n- and p-channel devices, respectively. Since no silicide was used, source and drain sheet resistance was about 200 Omega / Square Operator . Only one level of metal was used. Since no kink is observed in thin films, regular nshort and pshort SPICE models were used to simulate circuit operation. Circuits with the following performances were obtained at V/sub dd/=3.3 V: 2:1 multiplexer operating at 1.4 Gb/s (50 mW), voltage-controlled oscillator with an output frequency of up to 1.8 GHz (75 mW), and output stages with 250-ps rise and fall times (output impedance=25 Omega ). The output voltage swing is ECL, and a power dissipation of 65 mW is observed at a 312 Mb/s data rate. A 2:1 frequency divider operating with an input frequency of 2 GHz and dissipating 12 mW was fabricated. Simulation indicates 3-GHz operation if silicide is used and higher speed performance if the circuit is realized with two metal levels.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"2008 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127317685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Threshold voltage and transconductance of fully depleted thin-film SOI MOSFETs 全耗尽薄膜SOI mosfet的阈值电压和跨导

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95414

C. Lee, P. Wyatt

{"title":"Threshold voltage and transconductance of fully depleted thin-film SOI MOSFETs","authors":"C. Lee, P. Wyatt","doi":"10.1109/SOI.1988.95414","DOIUrl":"https://doi.org/10.1109/SOI.1988.95414","url":null,"abstract":"Summary form only given. In lightly doped or near-intrinsic thin-film SOI MOSFETs, the Fermi potential phi /sub B/ is close to zero. If threshold is defined by extrapolation to zero current from the linear region, then at the threshold condition the concentration of free carriers close to the surface is not zero, and may be greater than that of impurity charges in these films. In this case simulation shows that the front-surface potential Psi /sub sf/, which is the band bending from a hypothetical neutral film body to the front surface, is substantially greater than 2 phi /sub B/. Therefore, the definition of threshold condition Psi /sub sf/=2 phi /sub B/ as the onset of strong inversion is not consistent with the experimental technique of determining threshold by extrapolation. The simulations indicate that critical surface-potential bending of phi /sub B/+0.35 V is required to reach the threshold condition at zero back-gate bias when phi /sub B/ is less than 0.35 V. This critical surface-potential bending is found to be a weak function of back-gate bias. The threshold voltage and surface potentials of fully depleted SOI MOSFETs at the threshold condition are not significantly affected by the presence of inversion-layer charge even if it is much greater than the impurity charge as in the case of lightly doped Si films. The front-gate linear transconductance is relatively insensitive to the back-gate device parameters even though the front-gate threshold voltage is dependent on them. Simulations show that the transconductance remains nearly constant up to about 10/sup 15/ cm/sup -3/ and then falls off rapidly with increasing doping concentration as a result of mobility degradation. The transconductance is independent of Si film thickness if the mobility effect is not significant and the source/drain resistance is not high enough to become the limiting factor.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126780716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Demonstration of the benefits of SOI for high temperature operation SOI在高温运行中的优势论证

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95439

W. Krull, J.C. Lee

{"title":"Demonstration of the benefits of SOI for high temperature operation","authors":"W. Krull, J.C. Lee","doi":"10.1109/SOI.1988.95439","DOIUrl":"https://doi.org/10.1109/SOI.1988.95439","url":null,"abstract":"Summary form only given. To evaluate the performance of SOI circuits at high temperatures, CMOS 4K SRAMs were fabricated on SIMOX (separation by implantation of oxygen) and bulk starting material. Four varieties were included in this study: bulk (5 mu m epi on n/sup +/), and SIMOX/SOI with three silicon-layer thicknesses (0.5 mu m, 0.75 mu m, and 1.0 mu m). This combination allows the assessment of three device structures: standard bulk devices, standard SOI devices (S/D contacting the buried oxide), and semi-bulk SOI devices which operate like bulk devices but are dielectrically isolated. All the SOI SRAMs were functional to the maximum temperature available, 300 degrees C. The bulk circuits also functioned at elevated temperatures, but lost functionality between 250 degrees C and 275 degrees C due to the rapidly increasing leakage current associated with the well junction. The synchronous access time increased approximately linearly with temperature for all devices, and was nearly twice the measured room-temperature value at 300 degrees C. Leakage current increased strongly with temperature for all devices, with the thin SOI devices having the least static current at the highest temperatures.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129825421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Drain junction leakage current in SIMOX/MOSFETs SIMOX/ mosfet漏极结漏电流

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95431

J. Hwang, P. McMullin, M. Hanes, D. Schmidt

{"title":"Drain junction leakage current in SIMOX/MOSFETs","authors":"J. Hwang, P. McMullin, M. Hanes, D. Schmidt","doi":"10.1109/SOI.1988.95431","DOIUrl":"https://doi.org/10.1109/SOI.1988.95431","url":null,"abstract":"Summary form only given. The drain junction leakage current, which is representative of the silicon film quality, can be separated from the subthreshold leakage by applying proper biases to the front and back gates. Preliminary results indicate that the junction leakage increases superlinearly with the drain voltage and cannot be explained by S-R-H generation. In addition, the leakage current shows two distinctive regions in the drain voltage. In the low voltage region, below 5 V, its voltage dependence is relatively weak. In the higher voltage region (but below the avalanche breakdown) the leakage depends much more strongly on the drain voltage. The junction leakage in the lower drain voltage region is also found to be very sensitive to temperature. Measurements of leakage as a function of temperature show that the activation energy slightly decreases with increasing voltage, indicating the lowering of an emission barrier by increasing electric field. This leakage current can be well explained by the Poole Frenkel emission model. More rigorous analyses indicate that the leakage mechanism is a mixture of field-enhanced thermal emission and thermally assisted field emission. Drain junction leakage in the higher voltage region shows a good fit to the Fowler-Nordheim field-emission model. Soft breakdown in p/n junction diodes containing metallic impurities has been ascribed to Fowler-Nordheim field emission due to localized high electric fields near metallic precipitates. This argument may be applicable to SIMOX/MOSFETs.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114961161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1