S. Malhi, M. Anderson, C.C. Shen, K. Bean, R. Sundaresan, G. Gopffarth, K. Lindberg, D. Yeakley, J. Smith
{"title":"全蚀刻层转移/绝缘体上硅(FELT/SOI)材料的特性","authors":"S. Malhi, M. Anderson, C.C. Shen, K. Bean, R. Sundaresan, G. Gopffarth, K. Lindberg, D. Yeakley, J. Smith","doi":"10.1109/SOI.1988.95396","DOIUrl":null,"url":null,"abstract":"Summary form only given. A full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material process has been developed that meets the following criteria: (1) the material quality is identical to epitaxial silicon layers; (2) the SOI layer thickness is well controlled; (3) the insulator material choice and thickness is variable; (4) the device-to-device isolation is left to customer discretion. In the FELT/SOI process, a p+ etchstop layer is fabricated on a lightly doped starting substrate followed by epitaxial layer deposition with the type and resistivity required for the final SOI layer. Next an insulator layer is either grown or deposited followed by thick polysilicon deposition as is typical in standard DI process. The original substrate is now mechanically ground up to the vicinity of p+ etchstop layer. The remaining silicon overlying the etchstop layer and the etchstop layer itself are then removed in doping sensitive etches followed by surface finish. The SOI layer thickness control over a nominally 10- mu m layer on a 4-in wafer is +or-0.5 mu m, and the layer shows no material defects. Bipolar transistors fabricated on this material and epitaxial control material show comparable performance in terms of high gain sharp junction breakdown, and good yield.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"273 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Characteristics of full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material\",\"authors\":\"S. Malhi, M. Anderson, C.C. Shen, K. Bean, R. Sundaresan, G. Gopffarth, K. Lindberg, D. Yeakley, J. Smith\",\"doi\":\"10.1109/SOI.1988.95396\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only given. A full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material process has been developed that meets the following criteria: (1) the material quality is identical to epitaxial silicon layers; (2) the SOI layer thickness is well controlled; (3) the insulator material choice and thickness is variable; (4) the device-to-device isolation is left to customer discretion. In the FELT/SOI process, a p+ etchstop layer is fabricated on a lightly doped starting substrate followed by epitaxial layer deposition with the type and resistivity required for the final SOI layer. Next an insulator layer is either grown or deposited followed by thick polysilicon deposition as is typical in standard DI process. The original substrate is now mechanically ground up to the vicinity of p+ etchstop layer. The remaining silicon overlying the etchstop layer and the etchstop layer itself are then removed in doping sensitive etches followed by surface finish. The SOI layer thickness control over a nominally 10- mu m layer on a 4-in wafer is +or-0.5 mu m, and the layer shows no material defects. Bipolar transistors fabricated on this material and epitaxial control material show comparable performance in terms of high gain sharp junction breakdown, and good yield.<<ETX>>\",\"PeriodicalId\":391934,\"journal\":{\"name\":\"Proceedings. SOS/SOI Technology Workshop\",\"volume\":\"273 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-10-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. SOS/SOI Technology Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.1988.95396\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. SOS/SOI Technology Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.1988.95396","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Characteristics of full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material
Summary form only given. A full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material process has been developed that meets the following criteria: (1) the material quality is identical to epitaxial silicon layers; (2) the SOI layer thickness is well controlled; (3) the insulator material choice and thickness is variable; (4) the device-to-device isolation is left to customer discretion. In the FELT/SOI process, a p+ etchstop layer is fabricated on a lightly doped starting substrate followed by epitaxial layer deposition with the type and resistivity required for the final SOI layer. Next an insulator layer is either grown or deposited followed by thick polysilicon deposition as is typical in standard DI process. The original substrate is now mechanically ground up to the vicinity of p+ etchstop layer. The remaining silicon overlying the etchstop layer and the etchstop layer itself are then removed in doping sensitive etches followed by surface finish. The SOI layer thickness control over a nominally 10- mu m layer on a 4-in wafer is +or-0.5 mu m, and the layer shows no material defects. Bipolar transistors fabricated on this material and epitaxial control material show comparable performance in terms of high gain sharp junction breakdown, and good yield.<>