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2019 IEEE 31st International Conference on Microelectronics (MIEL)最新文献

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Design of Non-Metastable SRAM Cells in 28 nm CMOS Technology 基于28纳米CMOS技术的非亚稳SRAM单元设计
2019 IEEE 31st International Conference on Microelectronics (MIEL) Pub Date : 2019-09-16 DOI: 10.1109/MIEL.2019.8889606
F. Crescioli, L. Frontini, V. Liberali, A. Stabile
{"title":"Design of Non-Metastable SRAM Cells in 28 nm CMOS Technology","authors":"F. Crescioli, L. Frontini, V. Liberali, A. Stabile","doi":"10.1109/MIEL.2019.8889606","DOIUrl":"https://doi.org/10.1109/MIEL.2019.8889606","url":null,"abstract":"This paper presents the design of an SRAM cell in 28 nm, specifically designed to avoid metastability at start-up. Metastable operation is avoided by unbalancing the size of transistors. Extensive simulations have confirmed that the probability of metastable operation is greatly reduced.","PeriodicalId":391606,"journal":{"name":"2019 IEEE 31st International Conference on Microelectronics (MIEL)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123096600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Blocking of Impacts of Single Ionizing Particles by CMOS C-Element in Two-Phase Systems 两相系统中CMOS C-Element阻挡单电离粒子冲击的研究
2019 IEEE 31st International Conference on Microelectronics (MIEL) Pub Date : 2019-09-01 DOI: 10.1109/MIEL.2019.8889609
V. Stenin, Yu. V. Katunin, K. A. Petrov
{"title":"Blocking of Impacts of Single Ionizing Particles by CMOS C-Element in Two-Phase Systems","authors":"V. Stenin, Yu. V. Katunin, K. A. Petrov","doi":"10.1109/MIEL.2019.8889609","DOIUrl":"https://doi.org/10.1109/MIEL.2019.8889609","url":null,"abstract":"The work presents the TCAD simulation of the 65 nm bulk CMOS C-element as resistant to the single-event transients. The charge collection from a track of a single nuclear particle simulates in impacted on drain regions of the transistors, which leads to the error pulses in the output of 2-phase inverters and C-element. The TCAD simulation used the tracks along the normal to the chip. The linear energy transfer from a particle to the track is 60 MeV.cm2/mg.","PeriodicalId":391606,"journal":{"name":"2019 IEEE 31st International Conference on Microelectronics (MIEL)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126091382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of Hsiao Decoders by Circuit-Level Minimization 基于电路级最小化的小型解码器优化
2019 IEEE 31st International Conference on Microelectronics (MIEL) Pub Date : 2019-09-01 DOI: 10.1109/MIEL.2019.8889623
K. Petrov, I. Danilov, A. S. Khazanova, M. Gorbunov
{"title":"Optimization of Hsiao Decoders by Circuit-Level Minimization","authors":"K. Petrov, I. Danilov, A. S. Khazanova, M. Gorbunov","doi":"10.1109/MIEL.2019.8889623","DOIUrl":"https://doi.org/10.1109/MIEL.2019.8889623","url":null,"abstract":"We showed that the Hsiao decoder circuit could be minimized, resulting in the delay or area reduction without significant increase of the decoder failure ratio. We designed three versions of the decoder (full, shortened and minimized) and showed that it is possible to reduce its delay time by 13–18%, or the area by 33–57% relative to the full version. Also, we showed using fault injection simulation that the value of the failure ratio varies from −8% to +6% for shortened and minimized versions relative to the full version.","PeriodicalId":391606,"journal":{"name":"2019 IEEE 31st International Conference on Microelectronics (MIEL)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122693523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Highly Parametrizable Chisel HCL Generator of Single-Path Delay Feedback FFT Processors 单径延迟反馈FFT处理器的高参数化凿形HCL发生器
2019 IEEE 31st International Conference on Microelectronics (MIEL) Pub Date : 2019-09-01 DOI: 10.1109/MIEL.2019.8889581
V. Milovanovic, M. Petrović
{"title":"A Highly Parametrizable Chisel HCL Generator of Single-Path Delay Feedback FFT Processors","authors":"V. Milovanovic, M. Petrović","doi":"10.1109/MIEL.2019.8889581","DOIUrl":"https://doi.org/10.1109/MIEL.2019.8889581","url":null,"abstract":"A configurable fast Fourier transform (FFT) engines and their inverse counterparts are indispensable in modern wireless communication and radar systems. The FFT processors are usually customized per use case. Therefore, a design generator of single-path delay feedback type of an FFT processor, that permits continuous input and output data streaming has been captured inside Chisel hardware construction language. It supports a wide range of parameter settings, like input data and twiddle factor widths, FFT sizes and number of stages, three radices, different scaling and rounding methods after each butterfly or dragonfly stage, among others, thus enabling an agile design space exploration. A comparison with commercially available FFTs which were specifically tailored for the particular FPGA platforms proves that FFT generator instances can be both performance-and resource-competitive with state of the art designs.","PeriodicalId":391606,"journal":{"name":"2019 IEEE 31st International Conference on Microelectronics (MIEL)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122956942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Experimental Estimation of Input Offset Voltage Radiation Degradation Rate in Bipolar Operational Amplifiers 双极运算放大器输入偏置电压辐射衰减率的实验估计
2019 IEEE 31st International Conference on Microelectronics (MIEL) Pub Date : 2019-09-01 DOI: 10.1109/MIEL.2019.8889637
A. Bakerenkov, V. Pershenkov, V. Felitsyn, A. Rodin, V. Telets, V. Belyakov, A. Zhukov, N. Gluhov
{"title":"Experimental Estimation of Input Offset Voltage Radiation Degradation Rate in Bipolar Operational Amplifiers","authors":"A. Bakerenkov, V. Pershenkov, V. Felitsyn, A. Rodin, V. Telets, V. Belyakov, A. Zhukov, N. Gluhov","doi":"10.1109/MIEL.2019.8889637","DOIUrl":"https://doi.org/10.1109/MIEL.2019.8889637","url":null,"abstract":"Radiation degradation rate of input offset voltage in bipolar operational amplifiers was estimated experimentally. High degradation rate was observed in devices with high input offset voltage initial values and temperature drifts. Obtained results were discussed.","PeriodicalId":391606,"journal":{"name":"2019 IEEE 31st International Conference on Microelectronics (MIEL)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127673531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Approximate Adder with Reduced Error 误差减小的近似加法器
2019 IEEE 31st International Conference on Microelectronics (MIEL) Pub Date : 2019-09-01 DOI: 10.1109/MIEL.2019.8889605
P. Balasubramanian, D. Maskell, K. Prasad
{"title":"Approximate Adder with Reduced Error","authors":"P. Balasubramanian, D. Maskell, K. Prasad","doi":"10.1109/MIEL.2019.8889605","DOIUrl":"https://doi.org/10.1109/MIEL.2019.8889605","url":null,"abstract":"A new approximate adder is proposed, which is suitable for FPGA-and ASIC-based implementations. Here, we consider an Artix-7 FPGA for the implementations using Vivado 2018.3. For 32-bit addition, the proposed approximate adder with an 8-bit least significant inaccurate sub-adder reports an improvement in the maximum frequency by 7.7% compared to the native accurate FPGA adder while consuming 22% fewer LUTs and 18.6% fewer registers. For 64-bit addition, the proposed approximate adder reports an increase in the maximum frequency by 9.1% than the accurate FPGA adder while consuming 11% fewer LUTs and 9.3% fewer registers. The power-delay product (PDP) is computed as the product of total on-chip power consumption and the minimum clock period. The proposed approximate adder achieves 14.7% and 9.3% reductions in PDP compared to the accurate FPGA adder for 32- and 64-bit additions respectively. Further, in comparison with a recent approximate adder presented in the literature, the proposed approximate adder reports a 40% reduction in the root mean square error (RMSE) while having the same design metrics.","PeriodicalId":391606,"journal":{"name":"2019 IEEE 31st International Conference on Microelectronics (MIEL)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125720663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Correlation between Temperature and Dose Rate Dependences of Input Bias Current Degradation in Bipolar Operational Amplifiers 双极运算放大器中输入偏置电流衰减的温度和剂量率相关性
2019 IEEE 31st International Conference on Microelectronics (MIEL) Pub Date : 2019-09-01 DOI: 10.1109/MIEL.2019.8889589
A. Bakerenkov, V. Pershenkov, V. Felitsyn, A. Rodin, V. Telets, V. Belyakov, A. Zhukov, N. Gluhov
{"title":"Correlation between Temperature and Dose Rate Dependences of Input Bias Current Degradation in Bipolar Operational Amplifiers","authors":"A. Bakerenkov, V. Pershenkov, V. Felitsyn, A. Rodin, V. Telets, V. Belyakov, A. Zhukov, N. Gluhov","doi":"10.1109/MIEL.2019.8889589","DOIUrl":"https://doi.org/10.1109/MIEL.2019.8889589","url":null,"abstract":"It was demonstrated experimentally that in ELDRS-susceptible operational amplifiers elevated temperature irradiation increases degradation rate of input bias current, while in ELDRS-free devices degradation rates at room and elevated temperatures are approximately equal.","PeriodicalId":391606,"journal":{"name":"2019 IEEE 31st International Conference on Microelectronics (MIEL)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131785193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Modeling Errors of the MISFET-Based Sensors' Characteristics 基于misfet的传感器特性建模误差
2019 IEEE 31st International Conference on Microelectronics (MIEL) Pub Date : 2019-09-01 DOI: 10.1109/MIEL.2019.8889573
B. Podlepetsky, N. Samotaev
{"title":"Modeling Errors of the MISFET-Based Sensors' Characteristics","authors":"B. Podlepetsky, N. Samotaev","doi":"10.1109/MIEL.2019.8889573","DOIUrl":"https://doi.org/10.1109/MIEL.2019.8889573","url":null,"abstract":"The accuracy of circuits', electrical and electrophysical models of MIS transistor sensors' elements, taking into account the errors of simplifying assumptions, approximations, extrapolations and experimental dispersions' characteristics in determining the parameters of the models and measured physical quantity is estimated.","PeriodicalId":391606,"journal":{"name":"2019 IEEE 31st International Conference on Microelectronics (MIEL)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131830760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modelling of ΔVT in NBT Stressed P-Channel Power VDMOSFETs NBT应力p沟道功率vdmosfet中ΔVT的建模
2019 IEEE 31st International Conference on Microelectronics (MIEL) Pub Date : 2019-09-01 DOI: 10.1109/MIEL.2019.8889584
N. Mitrović, D. Danković, Z. Prijić, N. Stojadinovic
{"title":"Modelling of ΔVT in NBT Stressed P-Channel Power VDMOSFETs","authors":"N. Mitrović, D. Danković, Z. Prijić, N. Stojadinovic","doi":"10.1109/MIEL.2019.8889584","DOIUrl":"https://doi.org/10.1109/MIEL.2019.8889584","url":null,"abstract":"Negative bias temperature instabilities in commercial IRF9520 p-channel power VDMOSFETs were studied in order to design an analytical model for this effect. A modelling framework is proposed, which tends to be in line with earlier obtained experimental data. Since the pulsed voltage stressing caused generally lower shifts as compared to static stressing performed at the same temperature with equal stress voltage magnitude, different kind of models are considered for static and pulsed stressing. Differences between static and pulsed NBT stress depend on both stress duty cycle and frequency, and the differences become more significant as the duty cycle decreases and frequency increases. Because of that, described model intent to apply to specific stress signal, but also to be adaptable to different types of stress signal. Modelling of threshold voltage shifts induced by pulsed negative bias temperature stress has been done on the bases of experimental results.","PeriodicalId":391606,"journal":{"name":"2019 IEEE 31st International Conference on Microelectronics (MIEL)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131669392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Algorithm for Restructuring of Structurally Synthesized BDDs 结构合成bdd的重构算法
2019 IEEE 31st International Conference on Microelectronics (MIEL) Pub Date : 2019-09-01 DOI: 10.1109/MIEL.2019.8889578
L. Jürimägi, R. Ubar
{"title":"Algorithm for Restructuring of Structurally Synthesized BDDs","authors":"L. Jürimägi, R. Ubar","doi":"10.1109/MIEL.2019.8889578","DOIUrl":"https://doi.org/10.1109/MIEL.2019.8889578","url":null,"abstract":"In this paper, we present a method for synthesizing Shared Structurally Synthesized BDDs $(mathrm{S}^{3}mathrm{BDD})$ for representing digital circuits with the goal of speeding up fault simulation. As the core of the method, we propose a novel algorithm to restructure the Structurally Synthesized BDDs (SSBDDs) [1], [2] into a form, which allows iterative embedding of SSBDDs, and compressing a set of SSBDDs into a single Shared SSBDD $(mathrm{S}^{3}mathrm{BDD})$ [3]. The target of such a compression of the $mathrm{S}^{3}mathrm{BDD}$ model, representing a digital circuit, is to reduce the memory requirements of the model. Experiments with proposed algorithm, applied to three families of benchmark circuits, demonstrate feasibility of the proposed method, its high scalability, and considerable speedup in fault simulation compared to the initial SSBDD model.","PeriodicalId":391606,"journal":{"name":"2019 IEEE 31st International Conference on Microelectronics (MIEL)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115743253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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