Algorithm for Restructuring of Structurally Synthesized BDDs

In this paper, we present a method for synthesizing Shared Structurally Synthesized BDDs $(\mathrm{S}^{3}\mathrm{BDD})$ for representing digital circuits with the goal of speeding up fault simulation. As the core of the method, we propose a novel algorithm to restructure the Structurally Synthesized BDDs (SSBDDs) [1], [2] into a form, which allows iterative embedding of SSBDDs, and compressing a set of SSBDDs into a single Shared SSBDD $(\mathrm{S}^{3}\mathrm{BDD})$ [3]. The target of such a compression of the $\mathrm{S}^{3}\mathrm{BDD}$ model, representing a digital circuit, is to reduce the memory requirements of the model. Experiments with proposed algorithm, applied to three families of benchmark circuits, demonstrate feasibility of the proposed method, its high scalability, and considerable speedup in fault simulation compared to the initial SSBDD model.