Optimization of Hsiao Decoders by Circuit-Level Minimization

Abstract

We showed that the Hsiao decoder circuit could be minimized, resulting in the delay or area reduction without significant increase of the decoder failure ratio. We designed three versions of the decoder (full, shortened and minimized) and showed that it is possible to reduce its delay time by 13–18%, or the area by 33–57% relative to the full version. Also, we showed using fault injection simulation that the value of the failure ratio varies from −8% to +6% for shortened and minimized versions relative to the full version.