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8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings最新文献

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The effect of DMOS cell geometry on the integrated current sensors of high-voltage power MOSFETs DMOS单元几何形状对高压功率mosfet集成电流传感器的影响
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509478
R. Zhu, T. P. Chow
{"title":"The effect of DMOS cell geometry on the integrated current sensors of high-voltage power MOSFETs","authors":"R. Zhu, T. P. Chow","doi":"10.1109/ISPSD.1996.509478","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509478","url":null,"abstract":"The integrated current-sensing power MOSFET is used in power electronics to implement system control, protective and diagnostic function. This paper compares integrated current-sensing power MOSFETs with the square (SQ) and atomic-lattice-layout (ALL) design. It is shown that the ALL design offers better performance than that with the SQ cell design.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126948722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The DI lateral insulated gate field controlled thyristor (LIGFT) DI侧绝缘栅场控可控硅
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509497
R. Sunkavalli, A. Tamba, B. J. Baliga
{"title":"The DI lateral insulated gate field controlled thyristor (LIGFT)","authors":"R. Sunkavalli, A. Tamba, B. J. Baliga","doi":"10.1109/ISPSD.1996.509497","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509497","url":null,"abstract":"A new device called the DI Lateral insulated Field Controlled Thyristor (LIGFT) is introduced, which eliminates the parasitic thyristor latchup problem of the LIGBT. The LIGFT successfully integrates a high voltage lateral FCT with a series low voltage lateral MOSFET to create a unique MOS-gate controlled three terminal device. In comparison to the LIGBT, the LIGFT is experimentally shown to achieve a tremendous increase in maximum controllable current (RBSOA) and FBSOA by eliminating parasitic thyristor latchup, at the expense of an increase in on-state voltage drop.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130870636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Self-enclosed vs. LOPOS-terminated lateral planar p/sup +/n and n/sup +/p junctions in 3C-SiC/Si 自封闭与lopos端接的3C-SiC/Si侧平面p/sup +/n和n/sup +/p结
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509461
R. Tyagi, T. Chow
{"title":"Self-enclosed vs. LOPOS-terminated lateral planar p/sup +/n and n/sup +/p junctions in 3C-SiC/Si","authors":"R. Tyagi, T. Chow","doi":"10.1109/ISPSD.1996.509461","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509461","url":null,"abstract":"Lateral p/sup +/n and n/sup +/p diodes in 3C-SiC/Si, with different isolation terminations, have been compared at both room and elevated temperatures, up to 250/spl deg/C. The ion-implanted, planar diodes have been demonstrated with leakage currents as low as 2.65/spl times/10/sup -6/ A/cm/sup 2/ at room temperature, the lowest known for 3C-SiC. The forward drop for N-implanted junctions is found to be tightly distributed at 1.6-1.7 V, and that for Al-implanted diodes around 1.7-1.9 V. The ideality factor for the diodes is found to lie between 1.8 and 2.5. The N-implanted diodes show better reverse leakage characteristics than the Al-implanted junctions, with almost an order of magnitude lower leakage current. Two different termination schemes, self-enclosed vs. LOPOS-terminated, have been compared for the two diodes. Specific contact resistivity, as low as 1/spl times/10/sup -7/ /spl Omega/-cm/sup 2/ is obtained for ohmic contacts to the implanted regions.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133752707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Thermal management and design aspects of high performance plastic quad flat packages for smart-power ICs 智能功率ic高性能塑料四平面封装的热管理和设计方面
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509489
M. Kasem
{"title":"Thermal management and design aspects of high performance plastic quad flat packages for smart-power ICs","authors":"M. Kasem","doi":"10.1109/ISPSD.1996.509489","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509489","url":null,"abstract":"This paper investigates the influence of the design and physical limitations on the performance of thin quad flat packages (TQFIPs). In particular, the evaluation and implementation methodology for low profile 48-lead TQFPs is outlined. A 3-D finite element scheme to simulate the thermal effects of different design configurations and material properties has been developed. Thermal design guidelines which provide quantitative understanding for package thermal management will be summarized. Also, this paper highlights the qualification test results which have proven that this package has an excellent reliability performance when compared to the current industry standards. An improvement by a factor of 6 in die attach shear strength has been achieved. In addition, C-SAM analysis of parts exposed to pre-conditioning and HAST tests revealed that these new packages have very high cracking and moisture penetration resistance characteristics.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128222265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The dual-gate MOS controlled thyristor with current saturation capability 具有电流饱和能力的双栅MOS控制晶闸管
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509465
M. Mehrotra, B. J. Baliga
{"title":"The dual-gate MOS controlled thyristor with current saturation capability","authors":"M. Mehrotra, B. J. Baliga","doi":"10.1109/ISPSD.1996.509465","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509465","url":null,"abstract":"A new power device structure that combines the characteristics of the MCT and the IGBT is described. The dual-gate MCT behaves as an IGBT or an MCT depending upon the bias applied to one of the gates. Devices with 700 V blocking capability were fabricated and experimentally demonstrated to exhibit low on-state voltage drop in the MCT mode and good FBSOA characteristics in the IGBT mode. Measured on-state voltage drops of 1.5 V were obtained for the thyristor mode with a turn-off time of 15 /spl mu/s. The device transits from the thyristor mode to the IGBT mode in 6 /spl mu/s. No lifetime killing technique was used to control the turn-off time for these devices.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128244041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Undamped inductive switching of integrated quasi-vertical DMOSFETs 集成准垂直dmosfet的无阻尼电感开关
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509485
R. Constapel, M. S. Shekar, R.K. Williams
{"title":"Undamped inductive switching of integrated quasi-vertical DMOSFETs","authors":"R. Constapel, M. S. Shekar, R.K. Williams","doi":"10.1109/ISPSD.1996.509485","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509485","url":null,"abstract":"This investigation explores the unclamped inductive switching (UIS) performance and failure mechanisms of 60 V quasi-vertical N-channel DMOSFETs through measurement and numerical device simulation. The non-uniform current distributions that arise inside the DMOS during UIS are analyzed and the effects of local self-heating are investigated.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123181308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
LDMOS implementation by large tilt implant in 0.6 /spl mu/m BCD5 process, flash memory compatible LDMOS实现采用大倾角植入0.6 /spl mu/m的BCD5工艺，兼容闪存
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509452
C. Contiero, P. Galbiati, M. Palmieri, L. Vecchi
{"title":"LDMOS implementation by large tilt implant in 0.6 /spl mu/m BCD5 process, flash memory compatible","authors":"C. Contiero, P. Galbiati, M. Palmieri, L. Vecchi","doi":"10.1109/ISPSD.1996.509452","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509452","url":null,"abstract":"This paper describes a method for integrating power LDMOS structures in a smart power Bipolar-CMOS-DMOS technology called BCD5 designed at 0.6 /spl mu/m, compatible with VLSI EPROM, EEPROM and flash non volatile memories (NVM). The compatibility between NVM and LDMOS is achieved replacing conventional DMOS manufacturing processes, consisting of high temperature diffusion steps, with an innovative approach that exploits large angle of tilt implantation technique.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123892365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
The dual gate EST: a new MOS-gated thyristor structure 双栅EST:一种新型mos门控晶闸管结构
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509463
S. Sawant, S. Sridhar, B. J. Baliga
{"title":"The dual gate EST: a new MOS-gated thyristor structure","authors":"S. Sawant, S. Sridhar, B. J. Baliga","doi":"10.1109/ISPSD.1996.509463","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509463","url":null,"abstract":"In this paper, the characteristics of a new MOS-gated thyristor-the Dual Gate Emitter Switched Thyristor (DG-EST)-are presented. The DG-EST consists of a Dual Channel Emitter Switched Thyristor (DC-EST) section and a Conventional Emitter Switched Thyristor (C-EST) section with a common main thyristor region that can be controlled using two independent gate electrodes. This device has a lower on-state voltage drop than the C-EST and at the same time possesses the high voltage current saturation feature of the DC-EST. The DG-EST has been found to exhibit a much higher parasitic thyristor latch-up current density than the C-EST and the DC-EST structures and has a superior trade-off curve between on-state voltage drop and turn-off time when compared to the C-EST structure.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128999671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ADFET-a simple inexpensive power device adfet是一种简单廉价的功率器件
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509504
F. Robb
{"title":"ADFET-a simple inexpensive power device","authors":"F. Robb","doi":"10.1109/ISPSD.1996.509504","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509504","url":null,"abstract":"A new high-voltage power device, termed the ADFET for alloyed drain power MOSFET, provides an economical alternative to conventional power MOSFETs (epi-FETs) for many applications. Possessing qualities mid-way between a non-punchthrough (NPT) IGBT and an epitaxial power MOSFET, 1200 V ADFETs have on-voltages about half that of 1200 V epi-FETs and fall times of /spl sim/90 nsec. In addition, ADFET costs are dramatically lower than epi-FETs, not just because lower on-voltages reduce die sizes, but also because the floatzone (FZ) starting material is much less expensive than thick epitaxial layers. This paper discusses fabrication of the ADFET, provides actual 1200 V TO-220 device data with direct comparison to non-punchthrough IGBT and epitaxial power MOSFET data, and reviews MEDICI modeling performed to elucidate mechanisms.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132179305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Monolithic integration of the vertical IGBT and intelligent protection circuits 单片集成垂直IGBT和智能保护电路
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509501
Z. Shen, S. P. Robb
{"title":"Monolithic integration of the vertical IGBT and intelligent protection circuits","authors":"Z. Shen, S. P. Robb","doi":"10.1109/ISPSD.1996.509501","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509501","url":null,"abstract":"In this paper, we have developed a new smart discrete technology to monolithically integrate the high voltage vertical IGBT with low-voltage NMOS protection circuitry by adding a p-well step to the conventional IGBT process. Two new 600 V intelligent IGBTs, based on the same technology but using different protection schemes, are reported for the first time. The first intelligent IGBT provides protection against over-current and over-temperature conditions. The second intelligent IGBT provides protection against short circuit conditions by means of sensing collector voltage. The typically observed characteristics of the intelligent IGBT's include a forward voltage of 1.4 V at a current density of 100 A/cm/sup 2/, a turn-off fall time of 200 ns, and a short-circuit withstand time at 125/spl deg/C of more than 50 /spl mu/s.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125384308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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