LDMOS实现采用大倾角植入0.6 /spl mu/m的BCD5工艺，兼容闪存

8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI:10.1109/ISPSD.1996.509452

C. Contiero, P. Galbiati, M. Palmieri, L. Vecchi

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引用次数: 25

摘要

本文介绍了一种将功率LDMOS结构集成到智能功率双极cmos - dmos技术BCD5中的方法，BCD5的设计速度为0.6 /spl mu/m，兼容VLSI EPROM、EEPROM和闪存非易失性存储器(NVM)。NVM和LDMOS之间的兼容性实现了取代传统的DMOS制造工艺，包括高温扩散步骤，利用创新的方法，利用大倾角植入技术。

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LDMOS implementation by large tilt implant in 0.6 /spl mu/m BCD5 process, flash memory compatible

This paper describes a method for integrating power LDMOS structures in a smart power Bipolar-CMOS-DMOS technology called BCD5 designed at 0.6 /spl mu/m, compatible with VLSI EPROM, EEPROM and flash non volatile memories (NVM). The compatibility between NVM and LDMOS is achieved replacing conventional DMOS manufacturing processes, consisting of high temperature diffusion steps, with an innovative approach that exploits large angle of tilt implantation technique.

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来源期刊

8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings

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