LDMOS implementation by large tilt implant in 0.6 /spl mu/m BCD5 process, flash memory compatible

Abstract

This paper describes a method for integrating power LDMOS structures in a smart power Bipolar-CMOS-DMOS technology called BCD5 designed at 0.6 /spl mu/m, compatible with VLSI EPROM, EEPROM and flash non volatile memories (NVM). The compatibility between NVM and LDMOS is achieved replacing conventional DMOS manufacturing processes, consisting of high temperature diffusion steps, with an innovative approach that exploits large angle of tilt implantation technique.