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2006 International Electron Devices Meeting最新文献

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Universality of Off-State Degradation in Drain Extended NMOS Transistors 漏极扩展NMOS晶体管非状态退化的普遍性
2006 International Electron Devices Meeting Pub Date : 2006-12-01 DOI: 10.1109/IEDM.2006.346895
D. Varghese, H. Kufluoglu, V. Reddy, H. Shichijo, S. Krishnan, M. A. Alam
{"title":"Universality of Off-State Degradation in Drain Extended NMOS Transistors","authors":"D. Varghese, H. Kufluoglu, V. Reddy, H. Shichijo, S. Krishnan, M. A. Alam","doi":"10.1109/IEDM.2006.346895","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346895","url":null,"abstract":"Off-state degradation in drain extended NMOS transistors is studied. It is shown that the damage is primarily due to Si-O bonds broken by hot carriers. These hot carriers are generated through impact ionization of surface band-to-band tunneling (BTBT) current. The resultant degradation is found to be universal, enabling reliability projections at lower stress voltages and based on shorter duration tests, than previously anticipated","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128208984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
High PAE 1mm AlGaN/GaN HEMTs for 20 W and 43% PAE X-band MMIC Amplifiers 用于20 W和43% PAE x波段MMIC放大器的高PAE 1mm AlGaN/GaN HEMTs
2006 International Electron Devices Meeting Pub Date : 2006-12-01 DOI: 10.1109/IEDM.2006.346801
J. Moon, D. Wong, M. Antcliffe, P. Hashimoto, M. Hu, P. Willadsen, M. Micovic, H. Moyer, A. Kurdoghlian, P. Macdonald, M. Wetzel, R. Bowen
{"title":"High PAE 1mm AlGaN/GaN HEMTs for 20 W and 43% PAE X-band MMIC Amplifiers","authors":"J. Moon, D. Wong, M. Antcliffe, P. Hashimoto, M. Hu, P. Willadsen, M. Micovic, H. Moyer, A. Kurdoghlian, P. Macdonald, M. Wetzel, R. Bowen","doi":"10.1109/IEDM.2006.346801","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346801","url":null,"abstract":"This work represents state-of-the-art performances of both large gateperiphery discrete GaN HEMTs devices and its application toward GaN MMICs amplifiers with state-of-the-art performances in simultaneous output power, PAE, and MMIC power density","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130478977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Nonvolatile SRAM Cell 非易失性SRAM单元
2006 International Electron Devices Meeting Pub Date : 2006-12-01 DOI: 10.1109/IEDM.2006.346730
W. Wang, A. Gibby, Z. Wang, Tze Wee Chen, S. Fujita, P. Griffin, Y. Nishi, S. Wong
{"title":"Nonvolatile SRAM Cell","authors":"W. Wang, A. Gibby, Z. Wang, Tze Wee Chen, S. Fujita, P. Griffin, Y. Nishi, S. Wong","doi":"10.1109/IEDM.2006.346730","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346730","url":null,"abstract":"A nonvolatile SRAM cell with two back-up nonvolatile memory devices is proposed. This novel cell offers nonvolatile storage, thus allowing selected blocks of SRAM to be powered down during operation. There is no area penalty. A slight performance penalty is anticipated","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124646653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
Single Metal Gate on High-k Gate Stacks for 45nm Low Power CMOS 45nm低功耗CMOS高k栅极堆叠的单金属栅极
2006 International Electron Devices Meeting Pub Date : 2006-12-01 DOI: 10.1109/IEDM.2006.346861
W. Taylor, C. Capasso, B. Min, B. Winstead, E. Verret, K. Loiko, D. Gilmer, R. Hegde, J. Schaeffer, E. Luckowski, A. Martínez, M. Raymond, C. Happ, D. Triyoso, S. Kalpat, A. Haggag, D. Roan, J. Nguyen, L. La, L. Hebert, J. Smith, D. Jovanovic, D. Burnett, M. Foisy, N. Cave, P. Tobin, S. Samavedam, S. B. White, S. Venkatesan
{"title":"Single Metal Gate on High-k Gate Stacks for 45nm Low Power CMOS","authors":"W. Taylor, C. Capasso, B. Min, B. Winstead, E. Verret, K. Loiko, D. Gilmer, R. Hegde, J. Schaeffer, E. Luckowski, A. Martínez, M. Raymond, C. Happ, D. Triyoso, S. Kalpat, A. Haggag, D. Roan, J. Nguyen, L. La, L. Hebert, J. Smith, D. Jovanovic, D. Burnett, M. Foisy, N. Cave, P. Tobin, S. Samavedam, S. B. White, S. Venkatesan","doi":"10.1109/IEDM.2006.346861","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346861","url":null,"abstract":"We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45nm low power (LP) CMOS technology. Inversion Tox (Tinv) values of 16Aring/18Aring (NMOS/PMOS) result in gate leakage current densities of 0.1/0.01 A/cm 2 and enable self-heated drive currents of 850/325muA/mum at 1nA/mum off-state leakage and Vdd=1V (900/340muA/mum non-self-heated). Additionally, the NMOS drive current of 1550 muA/mum (1650muA/mum non-self-heated) at an Ioff = 100nA/mum and Vdd=1.2V is the highest reported for a hafnium-based high-k gate stack. The approach is compatible with a dual-gate oxide (DGO) module for I/O devices and allows optimization for performance and power typically only possible in triple gate oxide architectures","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122236224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
SiN Gate Dielectric with Oxygen-enriched Interface (OI-SiN) Utilizing Dual-core-SiON Technique for hp65-SoC LOP Application 基于双核技术的富氧界面SiN栅极介电介质在hp65-SoC LOP中的应用
2006 International Electron Devices Meeting Pub Date : 2006-12-01 DOI: 10.1109/IEDM.2006.347007
S. Tsujikawa, H. Umeda, T. Hayashi, K. Ohnishi, K. Shiga, K. Kawase, J. Yugami, H. Yoshimura, M. Yoneda
{"title":"SiN Gate Dielectric with Oxygen-enriched Interface (OI-SiN) Utilizing Dual-core-SiON Technique for hp65-SoC LOP Application","authors":"S. Tsujikawa, H. Umeda, T. Hayashi, K. Ohnishi, K. Shiga, K. Kawase, J. Yugami, H. Yoshimura, M. Yoneda","doi":"10.1109/IEDM.2006.347007","DOIUrl":"https://doi.org/10.1109/IEDM.2006.347007","url":null,"abstract":"A solution of utilizing an N-rich SiON gate dielectric toward achieving highly reliable pMOS is demonstrated. The solution consists of a combination of two techniques: (1) a SiN-based gate dielectric with oxygen-enriched interface (OI-SiN) enabling nMOS and pMOS characteristics superior to plasma-nitrided oxides (PNO) and (2) a dual-core-SiON technique in which SiON in pMOS is selectively thickened by fluorine ion implantation to the poly-Si layer with the aim of acquiring NBTI immunity. The latter improved the NBTI immunity of pMOS with OI-SiN gate dielectrics to a level comparable to that with conventional PNO. Although the thickening of SiON using dual-core-SiON technique naturally decreases pMOS on-current, the performance remains superior to that with PNO","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114631042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
1 nm NiSi/Si Junction Design based on First-Principles Calculation for Ultimately Low Contact Resistance 基于第一性原理计算的低接触电阻1nm NiSi/Si结设计
2006 International Electron Devices Meeting Pub Date : 2006-12-01 DOI: 10.1109/IEDM.2006.346791
T. Yamauchi, A. Kinoshita, Y. Tsuchiya, J. Koga, K. Kato
{"title":"1 nm NiSi/Si Junction Design based on First-Principles Calculation for Ultimately Low Contact Resistance","authors":"T. Yamauchi, A. Kinoshita, Y. Tsuchiya, J. Koga, K. Kato","doi":"10.1109/IEDM.2006.346791","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346791","url":null,"abstract":"This paper studies the Schottky barrier height (SBH) modulation effect induced by dipoles generation at the nickel silicide (NiSi)/silicon (Si) interface, based on first-principles calculations. Dipole comforting SBH is dramatically reduced to 0.1 eV in 1 nm region around the interface for the case of B atoms substituted for Si atoms. The results suggest that NiSi with appropriate dopant preparation is a plausible electrode material for ultimately small p-MOSFETs","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128215028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Performance Boost using a New Device Design Methodology Based on Characteristic Current for Low-Power CMOS 基于特性电流的低功耗CMOS器件设计新方法的性能提升
2006 International Electron Devices Meeting Pub Date : 2006-12-01 DOI: 10.1109/IEDM.2006.346995
E. Yoshida, Y. Momiyama, M. Miyamoto, T. Saiki, M. Kojima, S. Satoh, T. Sugii
{"title":"Performance Boost using a New Device Design Methodology Based on Characteristic Current for Low-Power CMOS","authors":"E. Yoshida, Y. Momiyama, M. Miyamoto, T. Saiki, M. Kojima, S. Satoh, T. Sugii","doi":"10.1109/IEDM.2006.346995","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346995","url":null,"abstract":"The authors proposes a characteristic current (I_chr) to replace the conventional saturation drive current used to estimate approximate CMOS inverter delay times for deeply scaled devices. The authors also present a new device design method based on I_chr to achieve a higher operation frequency for CMOS inverter circuits. The new method shortens propagation delay time (Tpd) by 15%","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130883127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
1.8 mΩcm2, 10 A Power MOSFET in 4H-SiC 1.8 mΩcm2, 10a功率MOSFET, 4H-SiC
2006 International Electron Devices Meeting Pub Date : 2006-12-01 DOI: 10.1109/IEDM.2006.346929
S. Harada, M. Kato, K. Suzuki, M. Okamoto, T. Yatsuo, K. Fukuda, K. Arai
{"title":"1.8 mΩcm2, 10 A Power MOSFET in 4H-SiC","authors":"S. Harada, M. Kato, K. Suzuki, M. Okamoto, T. Yatsuo, K. Fukuda, K. Arai","doi":"10.1109/IEDM.2006.346929","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346929","url":null,"abstract":"The power MOSFET on 4H-SiC is an attractive high-speed and low-dissipation power switching device. The problem to be solved before realizing the 4H-SiC power MOSFET with low on-resistance is low channel mobility at the SiO2/SiC interface. This work has succeeded in increasing the channel mobility in the buried channel IEMOSFET on carbon-face substrate, and has achieved an extremely low on-resistance of 1.8 mΩcm2 with a blocking voltage of 660 V","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131244168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
WireFET Technology for 3-D Integrated Circuits 用于三维集成电路的WireFET技术
2006 International Electron Devices Meeting Pub Date : 2006-12-01 DOI: 10.1109/IEDM.2006.346982
V. Varadarajan, Y. Yasuda, S. Balasubramanian, T. Liu
{"title":"WireFET Technology for 3-D Integrated Circuits","authors":"V. Varadarajan, Y. Yasuda, S. Balasubramanian, T. Liu","doi":"10.1109/IEDM.2006.346982","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346982","url":null,"abstract":"A novel method to fabricate a transistor directly within a wire is presented. The phenomenon of aluminum-induced crystallization of silicon is used to embed crystalline Si regions within an aluminum wire, enabling FETs to be fabricated directly within interconnects. The wireFET fabrication process is relatively simple, does not require unconventional materials or processing methods, and has low associated thermal budget (Tmax les 400 degC), so that it can be a cost-effective method for implementing 3-dimensionally integrated circuits","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133869981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node 基于ILD和TANOS结构的三维堆叠NAND快闪记忆体技术
2006 International Electron Devices Meeting Pub Date : 2006-12-01 DOI: 10.1109/IEDM.2006.346902
Soon-Moon Jung, J. Jang, W. Cho, Hoosung Cho, Jaehun Jeong, Youngchul Chang, Jonghyuk Kim Youngseop Rah, Y. Son, Junbeom Park, Minsung Song, Kyoung-Hoon Kim, Jm-Soo Lim, Kinam Kim
{"title":"Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node","authors":"Soon-Moon Jung, J. Jang, W. Cho, Hoosung Cho, Jaehun Jeong, Youngchul Chang, Jonghyuk Kim Youngseop Rah, Y. Son, Junbeom Park, Minsung Song, Kyoung-Hoon Kim, Jm-Soo Lim, Kinam Kim","doi":"10.1109/IEDM.2006.346902","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346902","url":null,"abstract":"For the first time, the 3 dimensionally stacked NAND Flash memory, is developed by implementing S3 (single-crystal Si layer stacking) technology, which was used to develop S3 SRAM previously. The NAND cell arrays are formed on the ILD as well as on the bulk to double the memory density without increasing the chip size. The feasibility of the technology was proven by the successful operation of 32 bit NAND flash memory cell strings with 63nm dimension and TANOS structures. The novel NAND cell operational scheme, so called SBT (source-body tied) scheme, is presented to maximize the advantages of 3 dimensionally stacked NAND cell structures","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133918761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 107
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